RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.07.26 (Sawada.Y)
     - Seabas2VC707_20170726.xpr.zip - Latest
     - Seabas2VC707_20170707.xpr.zip - Data acquisition problem.
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
4. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Programming VC707 Virtex7 BPI Flash memory
     1. Generate a bitstream (.bit) file in the normal way.

1. 1. 1. Open Vivado Lab Edition
      2. Open Hardware Manager, open target board
      3. Tools > Add Configuration Memory Device

1. 1. 1. Click OK to "Do you want to program the configuration memory device now?"
      2. Add your .mcs file to the Configuration File field
      3. Hit OK
      4. Right click on device >> Boot from Configuration Memory Device
      5. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.

YARR

• Git : https://gitlab.cern.ch/YARR/YARR or https://github.com/Yarr
• Documentation : http://yarr.readthedocs.io/
• Hardware : XpressK7 Board

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

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