Difference: RD53ADAQdevelopment (1 vs. 25)

Revision 252018-02-09 - KojiNakamura

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META TOPICPARENT name="WebHome"

RD53A DAQ Development

Added:
>
>
 

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

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/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers
Deleted:
<
<		-- Ryo Nagai - 2016-10-17
 

FE-I4 Readout Test

* Gitlab repository

*

Line: 52 to 52
 
Changed:
<
<

Comments

>
>

RD53A probe card

RD53AProbeCard

 
Changed:
<
<
<--/commentPlugin-->
>
>		-- Ryo Nagai - 2016-10-17
 
META FILEATTACHMENT attachment="OFTC_0.pdf" attr="" comment="" date="1495691002" name="OFTC_0.pdf" path="OFTC_0.pdf" size="619576" user="AtlasjSilicon" version="1"
META FILEATTACHMENT attachment="OFTC_1.pdf" attr="" comment="" date="1495691074" name="OFTC_1.pdf" path="OFTC_1.pdf" size="1782077" user="AtlasjSilicon" version="1"

Revision 242017-08-18 - AtlasjSilicon

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META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 12 to 12
 

FE-I4 Readout Test

Changed:
<
<		Git
>
>		* Gitlab repository

*
 
  1. FPGA Hardware and Additional apparatuses
    • FPGA Hardware
      • Prerequisites
        Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
        Tool Version : Xilinx Vivado 2015.4 or later tools
        If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.

Line: 34 to 34
 
      • source : trunk/multi_chip_FEI4/Software_SEABAS2
      • SiTCP IP Address : Default (192.168.10.16)

    • How to config FEI4
Changed:
<
<
      • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
        Please refer to SEABAS2 DAQ Usages.

>
>
      • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
        Please refer to SEABAS2 DAQ Usages.

 
  1. Release
Changed:
<
<
  1. Notes

    • When you use the original conversion board, you need to change the pin assignment to comply with your board.
      (Default firmware is build for a setup of Osaka Univ.)
    • Already-known warnings
      • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
      • Unused registers.
    • Programming VC707 Virtex7 BPI Flash memory
      1. Generate a bitstream (.bit) file in the normal way.
      2. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
      3. Open Vivado Lab Edition
      4. Open Hardware Manager, open target board
      5. Tools > Add Configuration Memory Device
      6. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
      7. Click OK to "Do you want to program the configuration memory device now?"
      8. Add your .mcs file to the Configuration File field
      9. Hit OK
      10. Right click on device >> Boot from Configuration Memory Device
      11. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
>
>
 

YARR

Revision 232017-08-03 - AtlasjSilicon

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META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 10 to 11
 -- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

Added:
>
>		 Git
 
  1. FPGA Hardware and Additional apparatuses
    • FPGA Hardware
      • Prerequisites
        Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
        Tool Version : Xilinx Vivado 2015.4 or later tools
        If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.

Line: 41 to 44
 
      • Unused registers.
    • Programming VC707 Virtex7 BPI Flash memory
      1. Generate a bitstream (.bit) file in the normal way.
Changed:
<
<
      1. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
>
>
      1. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
 
      1. Open Vivado Lab Edition
      2. Open Hardware Manager, open target board
      3. Tools > Add Configuration Memory Device
Changed:
<
<
      1. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
>
>
      1. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
 
      1. Click OK to "Do you want to program the configuration memory device now?"
      2. Add your .mcs file to the Configuration File field
      3. Hit OK
      4. Right click on device >> Boot from Configuration Memory Device
      5. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
Deleted:
<
<
    • Status report
      • (6/29 17:30) Modify FIFOs type in DataStore module "Standard FIFO" to "Fist-Word Fall-Through", we can confirm signals from DataStore. Next step is TXFIFO control management. by Sawada
      • (6/29 12:00) It is found that DataStore module is bottleneck for readout data... by Sawada
      • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
      • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
      • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada
 

YARR

Revision 222017-07-26 - AtlasjSilicon

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META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 34 to 33
 
    • How to config FEI4
      • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
        Please refer to SEABAS2 DAQ Usages.

  1. Release
Changed:
<
<
>
>
 
  1. Notes

    • When you use the original conversion board, you need to change the pin assignment to comply with your board.
      (Default firmware is build for a setup of Osaka Univ.)
    • Already-known warnings

Revision 212017-07-13 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 58 to 58
 
      • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
      • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
      • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada
Added:
>
>

YARR

 

Tips

Revision 202017-07-07 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 34 to 34
 
    • How to config FEI4
      • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
        Please refer to SEABAS2 DAQ Usages.

  1. Release
Changed:
<
<
>
>
 
  1. Notes

    • When you use the original conversion board, you need to change the pin assignment to comply with your board.
      (Default firmware is build for a setup of Osaka Univ.)
    • Already-known warnings

Revision 192017-06-29 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 52 to 53
 
      1. Right click on device >> Boot from Configuration Memory Device
      2. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
    • Status report
Added:
>
>
      • (6/29 17:30) Modify FIFOs type in DataStore module "Standard FIFO" to "Fist-Word Fall-Through", we can confirm signals from DataStore. Next step is TXFIFO control management. by Sawada
 
      • (6/29 12:00) It is found that DataStore module is bottleneck for readout data... by Sawada
      • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
      • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada

Revision 182017-06-29 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 52 to 52
 
      1. Right click on device >> Boot from Configuration Memory Device
      2. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
    • Status report
Added:
>
>
      • (6/29 12:00) It is found that DataStore module is bottleneck for readout data... by Sawada
 
      • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
      • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
      • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Revision 172017-06-28 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 12 to 12
 

FE-I4 Readout Test

  1. FPGA Hardware and Additional apparatuses
    • FPGA Hardware
Changed:
<
<
      • Prerequisites
        Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
        Tool Version : Xilinx Vivado 2015.4 or later tools

        If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.

>
>
      • Prerequisites
        Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
        Tool Version : Xilinx Vivado 2015.4 or later tools
        If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.

 
Line: 24 to 24
 
        • Power supply for SEABAS2
          • VDDA: +1.5 V, current limit 0.7 A
          • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
Changed:
<
<
        • Ethernet cable x2 (One between a conversion board and a SCC should be metal shielded to match GNDs.)
>
>
        • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
 
  1. DAQ Software
Line: 39 to 39
 
    • Already-known warnings
      • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
      • Unused registers.
Added:
>
>
    • Programming VC707 Virtex7 BPI Flash memory
      1. Generate a bitstream (.bit) file in the normal way.
      2. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
      3. Open Vivado Lab Edition
      4. Open Hardware Manager, open target board
      5. Tools > Add Configuration Memory Device
      6. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
      7. Click OK to "Do you want to program the configuration memory device now?"
      8. Add your .mcs file to the Configuration File field
      9. Hit OK
      10. Right click on device >> Boot from Configuration Memory Device
      11. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
 
    • Status report
Changed:
<
<
      • (6/28) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
>
>
      • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
      • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
 
      • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada
Deleted:
<
<
 

Tips

Revision 162017-06-28 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 40 to 40
 
      • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
      • Unused registers.
    • Status report
Added:
>
>
      • (6/28) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
 
      • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada
    • Task

Revision 152017-06-27 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 37 to 37
 
  1. Notes

    • When you use the original conversion board, you need to change the pin assignment to comply with your board.
      (Default firmware is build for a setup of Osaka Univ.)
    • Already-known warnings
Changed:
<
<
      • Redundant IBUF can be ignored.
>
>
      • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
      • Unused registers.
 
    • Status report
      • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada
Added:
>
>
 

Tips

Revision 142017-06-27 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 20 to 20
 
      • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
        - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
      • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

    • Hardware setup
Changed:
<
<
      • Example

        VC707_setup.jpg

>
>
      • Example recipe
        • Power supply for SEABAS2
          • VDDA: +1.5 V, current limit 0.7 A
          • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
        • Ethernet cable x2 (One between a conversion board and a SCC should be metal shielded to match GNDs.)
        • SourceMeter for the silicon sensor

          VC707_setup.jpg
 
  1. DAQ Software
Changed:
<
<
      • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
        Please refer to SEABAS2 DAQ Usages.

>
>
      • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
        Please refer to SEABAS2 DAQ Usages.

 
  1. Release
  2. Notes

Revision 132017-06-26 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 11 to 10
 -- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

Changed:
<
<
  1. FPGA Hardware and Additional apparatuses
>
>
  1. FPGA Hardware and Additional apparatuses
 
    • FPGA Hardware
      • Prerequisites
        Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
        Tool Version : Xilinx Vivado 2015.4 or later tools

        If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.

    • FEI4B Single Chip Card
Changed:
<
<
>
>
    • RJ45/FMC - SLVS/LVDS Conversion Board
      • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
        - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
      • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

    • Hardware setup
      • Example

        VC707_setup.jpg

 
  1. DAQ Software
Added:
>
>
    • How to config FEI4
      • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
        Please refer to SEABAS2 DAQ Usages.

 
  1. Release
Changed:
<
<
  1. Notes (日本語暫定簡易版)

    • FMC LPCのピン配置は阪大で使用しているテスト用変換基板のピン配置に準拠しています。それ以外の変換基板を利用の際は制約ファイルを編集してピン配置を変更する必要があります。
    • 現在、論理合成時のエラーは既知のものです。無視して構いません。どうしても気になる方は修正をお願いします。
    • インプリメンテーション時にタイミング違反の警告メッセージが出ますが無視してください。重要でない場所です。
    • FEI4B SCCにConfigが通ることまで確認しています。こちらの動作の都合で、FEI4からの受信データをPCへTCPで転送できているかどうかは6/25時点でまだ未確認です(澤田)。
>
>
  1. Notes

    • When you use the original conversion board, you need to change the pin assignment to comply with your board.
      (Default firmware is build for a setup of Osaka Univ.)
    • Already-known warnings
      • Redundant IBUF can be ignored.
    • Status report
      • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada
 

Tips

Line: 67 to 73
 
META FILEATTACHMENT attachment="OFTC_ref_note.pdf" attr="" comment="" date="1495691192" name="OFTC_ref_note.pdf" path="OFTC_ref_note.pdf" size="48837" user="AtlasjSilicon" version="1"
META FILEATTACHMENT attachment="references.pdf" attr="" comment="" date="1495693148" name="references.pdf" path="references.pdf" size="892748" user="AtlasjSilicon" version="1"
META FILEATTACHMENT attachment="LVDS2SLVS_Pins.zip" attr="" comment="" date="1495793797" name="LVDS2SLVS_Pins.zip" path="LVDS2SLVS_Pins.zip" size="217304" user="AtlasjSilicon" version="1"
Added:
>
>
META FILEATTACHMENT attachment="FEI4BSCC.jpg" attr="h" comment="" date="1498471156" name="FEI4BSCC.jpg" path="FEI4BSCC.jpg" size="136127" user="AtlasjSilicon" version="1"
META FILEATTACHMENT attachment="VC707_setup.jpg" attr="h" comment="" date="1498471264" name="VC707_setup.jpg" path="VC707_setup.jpg" size="225804" user="AtlasjSilicon" version="1"

Revision 122017-06-26 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 7 to 8
 
/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers
Changed:
<
<		-- Ryo Nagai - 2016-10-17
>
>		-- Ryo Nagai - 2016-10-17
 

FE-I4 Readout Test

Changed:
<
<
  • Firmware for VC707 to readout FE-I4B SCC - 2017.06.12 (Sawada.Y)
    - Seabas2VC707_part1_20170612.xpr.zip - SiTCP <-> SIO_REG was modified.
    - Seabas2VC707_part1_20170613.xpr.zip
    - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.

  • 注意点(日本語暫定簡易版)
    1.VC707用のものなのでKC705を利用の際は、SiTCPのGMIIとSGMIIの変換部分は編集する必要があります。
    2.FMC LPCのピン配置は阪大で使用しているテスト用変換基板のピン配置に準拠しています。それ以外の変換基板を利用の際は制約ファイルを編集してピン配置を変更する必要があります。
    3.現在、論理合成時のエラーは既知のものです。無視して構いません。気になる方は修正をお願いします。
    4.インプリメンテーション時にタイミング違反の警告メッセージが出ますが無視してください。
    5.FEI4B SCCにConfigが通ることまで確認しています。FEI4からの受信データをPCへTCPで転送できているかどうかは6/25時点でまだ未確認です(澤田)。
    6.検証時、DAQソフトウェアは SEABAS2用のものをご利用ください。
    SiTCP IP Address : Default(192.168.10.16)
    source : trunk/multi_chip_FEI4/Software_SEABAS2

  • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
>
>
  1. FPGA Hardware and Additional apparatuses
    • FPGA Hardware
      • Prerequisites
        Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
        Tool Version : Xilinx Vivado 2015.4 or later tools

        If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.

    • FEI4B Single Chip Card
    • RJ45/FMC - SLVS/LVDS Conversion Board
  2. DAQ Software
  3. Release
  4. Notes (日本語暫定簡易版)

    • FMC LPCのピン配置は阪大で使用しているテスト用変換基板のピン配置に準拠しています。それ以外の変換基板を利用の際は制約ファイルを編集してピン配置を変更する必要があります。
    • 現在、論理合成時のエラーは既知のものです。無視して構いません。どうしても気になる方は修正をお願いします。
    • インプリメンテーション時にタイミング違反の警告メッセージが出ますが無視してください。重要でない場所です。
    • FEI4B SCCにConfigが通ることまで確認しています。こちらの動作の都合で、FEI4からの受信データをPCへTCPで転送できているかどうかは6/25時点でまだ未確認です(澤田)。
 

Tips

Line: 27 to 42
 

Comments

Changed:
<
<
<--/commentPlugin-->
>
>
<--/commentPlugin-->
 
META FILEATTACHMENT attachment="OFTC_0.pdf" attr="" comment="" date="1495691002" name="OFTC_0.pdf" path="OFTC_0.pdf" size="619576" user="AtlasjSilicon" version="1"
META FILEATTACHMENT attachment="OFTC_1.pdf" attr="" comment="" date="1495691074" name="OFTC_1.pdf" path="OFTC_1.pdf" size="1782077" user="AtlasjSilicon" version="1"

Revision 112017-06-25 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

RD53A DAQ Development

Introduction

Line: 11 to 10
 -- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

Changed:
<
<
>
>
  • Firmware for VC707 to readout FE-I4B SCC - 2017.06.12 (Sawada.Y)
    - Seabas2VC707_part1_20170612.xpr.zip - SiTCP <-> SIO_REG was modified.
    - Seabas2VC707_part1_20170613.xpr.zip
    - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.

  • 注意点(日本語暫定簡易版)
    1.VC707用のものなのでKC705を利用の際は、SiTCPのGMIIとSGMIIの変換部分は編集する必要があります。
    2.FMC LPCのピン配置は阪大で使用しているテスト用変換基板のピン配置に準拠しています。それ以外の変換基板を利用の際は制約ファイルを編集してピン配置を変更する必要があります。
    3.現在、論理合成時のエラーは既知のものです。無視して構いません。気になる方は修正をお願いします。
    4.インプリメンテーション時にタイミング違反の警告メッセージが出ますが無視してください。
    5.FEI4B SCCにConfigが通ることまで確認しています。FEI4からの受信データをPCへTCPで転送できているかどうかは6/25時点でまだ未確認です(澤田)。
    6.検証時、DAQソフトウェアは SEABAS2用のものをご利用ください。
    SiTCP IP Address : Default(192.168.10.16)
    source : trunk/multi_chip_FEI4/Software_SEABAS2

 

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