RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

FE-I4 Readout Test

* Gitlab repository

*

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.08.10 (Sawada.Y)
     - fei4readout_vc707_prj-1.1.xpr.zip - Latest

YARR

• Git : https://gitlab.cern.ch/YARR/YARR or https://github.com/Yarr
• Documentation : http://yarr.readthedocs.io/
• Hardware : XpressK7 Board

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4

1. Release
   
   

YARR

• Git : https://gitlab.cern.ch/YARR/YARR or https://github.com/Yarr
• Documentation : http://yarr.readthedocs.io/
• Hardware : XpressK7 Board

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.07.26 (Sawada.Y)
     - Seabas2VC707_20170726.xpr.zip - Latest
     - Seabas2VC707_20170707.xpr.zip - Data acquisition problem.
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
4. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Programming VC707 Virtex7 BPI Flash memory
     1. Generate a bitstream (.bit) file in the normal way.

1. 1. 1. Open Vivado Lab Edition
      2. Open Hardware Manager, open target board
      3. Tools > Add Configuration Memory Device

1. 1. 1. Click OK to "Do you want to program the configuration memory device now?"
      2. Add your .mcs file to the Configuration File field
      3. Hit OK
      4. Right click on device >> Boot from Configuration Memory Device
      5. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.

YARR

• Git : https://gitlab.cern.ch/YARR/YARR or https://github.com/Yarr
• Documentation : http://yarr.readthedocs.io/
• Hardware : XpressK7 Board

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   

1. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Programming VC707 Virtex7 BPI Flash memory
     1. Generate a bitstream (.bit) file in the normal way.
     2. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
     3. Open Vivado Lab Edition
     4. Open Hardware Manager, open target board
     5. Tools > Add Configuration Memory Device
     6. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
     7. Click OK to "Do you want to program the configuration memory device now?"
     8. Add your .mcs file to the Configuration File field
     9. Hit OK
     10. Right click on device >> Boot from Configuration Memory Device
     11. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
   • Status report
     • (6/29 17:30) Modify FIFOs type in DataStore module "Standard FIFO" to "Fist-Word Fall-Through", we can confirm signals from DataStore. Next step is TXFIFO control management. by Sawada
     • (6/29 12:00) It is found that DataStore module is bottleneck for readout data... by Sawada
     • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
     • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
     • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

YARR

• Git : https://gitlab.cern.ch/YARR/YARR or https://github.com/Yarr
• Documentation : http://yarr.readthedocs.io/
• Hardware : XpressK7 Board

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.07.07 (Sawada.Y)
     - Seabas2VC707_20170707.xpr.zip - Data acquisition problem.
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
4. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Programming VC707 Virtex7 BPI Flash memory
     1. Generate a bitstream (.bit) file in the normal way.
     2. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
     3. Open Vivado Lab Edition
     4. Open Hardware Manager, open target board
     5. Tools > Add Configuration Memory Device
     6. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
     7. Click OK to "Do you want to program the configuration memory device now?"
     8. Add your .mcs file to the Configuration File field
     9. Hit OK
     10. Right click on device >> Boot from Configuration Memory Device
     11. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
   • Status report
     • (6/29 17:30) Modify FIFOs type in DataStore module "Standard FIFO" to "Fist-Word Fall-Through", we can confirm signals from DataStore. Next step is TXFIFO control management. by Sawada
     • (6/29 12:00) It is found that DataStore module is bottleneck for readout data... by Sawada
     • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
     • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
     • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   

1. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Programming VC707 Virtex7 BPI Flash memory
     1. Generate a bitstream (.bit) file in the normal way.
     2. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
     3. Open Vivado Lab Edition
     4. Open Hardware Manager, open target board
     5. Tools > Add Configuration Memory Device
     6. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
     7. Click OK to "Do you want to program the configuration memory device now?"
     8. Add your .mcs file to the Configuration File field
     9. Hit OK
     10. Right click on device >> Boot from Configuration Memory Device
     11. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
   • Status report
     • (6/29 17:30) Modify FIFOs type in DataStore module "Standard FIFO" to "Fist-Word Fall-Through", we can confirm signals from DataStore. Next step is TXFIFO control management. by Sawada
     • (6/29 12:00) It is found that DataStore module is bottleneck for readout data... by Sawada
     • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
     • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
     • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.06.26 (Sawada.Y)
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
4. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Programming VC707 Virtex7 BPI Flash memory
     1. Generate a bitstream (.bit) file in the normal way.
     2. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
     3. Open Vivado Lab Edition
     4. Open Hardware Manager, open target board
     5. Tools > Add Configuration Memory Device
     6. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
     7. Click OK to "Do you want to program the configuration memory device now?"
     8. Add your .mcs file to the Configuration File field
     9. Hit OK
     10. Right click on device >> Boot from Configuration Memory Device
     11. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
   • Status report

• • • (6/29 12:00) It is found that DataStore module is bottleneck for readout data... by Sawada
    • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
    • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
    • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (To use 1000BASE-T, use a Cat 5 cable or later. One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.06.26 (Sawada.Y)
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
4. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Programming VC707 Virtex7 BPI Flash memory
     1. Generate a bitstream (.bit) file in the normal way.
     2. Run this TCL command inside Vivado:
        $ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
     3. Open Vivado Lab Edition
     4. Open Hardware Manager, open target board
     5. Tools > Add Configuration Memory Device
     6. Select this part:
        Name: mt28gu01gaax1e-bpi-x16
        Part: mt28gu01gaax1e
        Manufacturer: Micron
        Alias: 28f00ag18f
        Family: g18
        Type: bpi
        Density: 1024
        Width: x16
     7. Click OK to "Do you want to program the configuration memory device now?"
     8. Add your .mcs file to the Configuration File field
     9. Hit OK
     10. Right click on device >> Boot from Configuration Memory Device
     11. Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
   • Status report

• • • (6/28 16:00) Previous problem was solved. "KEEP HIERARCHY" attribute is needed to not to change the hirarchy when Vivado synthesis.
    • (6/28 10:00) IserdesWith8b10bDec has a bug. Problem is still not be found. Maybe 8b10b decoder module is not removed when running synthesis... by Sawada
    • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware

• • FEI4B Single Chip Card
    • Manual FE-I4B_V2.0.pdf -
    • Appearance
      
      
      
      
  • RJ45/FMC - SLVS/LVDS Conversion Board
    • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
      - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
    • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
      
      
  • Hardware setup
    • Example recipe
      • Power supply for SEABAS2
        • VDDA: +1.5 V, current limit 0.7 A
        • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)

• • • • SourceMeter for the silicon sensor
        
        

1. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
2. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.06.26 (Sawada.Y)
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
3. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.

• • Status report

• • • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.06.26 (Sawada.Y)
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
4. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
     • Unused registers.
   • Status report

• • • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada
  • Task
    • Configuration from BPI flash memory
      ref : Programming VC707 Virtex7 BPI flash

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup
     • Example recipe
       • Power supply for SEABAS2
         • VDDA: +1.5 V, current limit 0.7 A
         • VDDD: +1.5 V, current limit 0.4 A (Not : 1.2 V!!)
       • Ethernet cable x2 (One between a conversion board and a SCC should be metal shielded to match GNDs.)
       • SourceMeter for the silicon sensor
         
         
2. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4
     • For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
       Please refer to SEABAS2 DAQ Usages.
       
       
3. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.06.26 (Sawada.Y)
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
4. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings

• • Status report
    • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

1. FPGA Hardware and Additional apparatuses
   • FPGA Hardware
     • Prerequisites
       Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
       Tool Version : Xilinx Vivado 2015.4 or later tools
       
       If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
       
       
   • FEI4B Single Chip Card
     • Manual FE-I4B_V2.0.pdf -
     • Appearance
       
       
       
       
   • RJ45/FMC - SLVS/LVDS Conversion Board
     • TB-FMCL-PH board (inrevium TOKYO ELECTRON DEVICE)
       - used for conversion between Samtec FMC connector (Low-Pin Count) and 2.54mm pitch pin header.
     • SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip
       
       
   • Hardware setup

1. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       
   • How to config FEI4

1. Release
   
   
   • Firmware for VC707 to readout FE-I4B SCC - 2017.06.26 (Sawada.Y)
     - Seabas2VC707_20170626.xpr.zip - Suppress critical warnings due to timing violations...
     - Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.
     
     
2. Notes
   
   
   • When you use the original conversion board, you need to change the pin assignment to comply with your board.
     (Default firmware is build for a setup of Osaka Univ.)
   • Already-known warnings
     • Redundant IBUF can be ignored.
   • Status report
     • (6/26) Succeeded in configuring FE-I4B and confirmed the response of the data signal. Problems remain in iserdes, 8b10b decoder part. by Sawada

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

• • FPGA Hardware
    • Prerequisites
      Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2)
      Tool Version : Xilinx Vivado 2015.4 or later tools
      
      If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
      
      
  • FEI4B Single Chip Card

1. DAQ Software
   
   
   • SEABAS DAQ for ATLAS Pixel Upgrade
     • source : trunk/multi_chip_FEI4/Software_SEABAS2
     • SiTCP IP Address : Default (192.168.10.16)
       
       

1. Release
   
   

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

FE-I4 Readout Test

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

• SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

• SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

• SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

• SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

• SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

• Firmware for VC707 to readout FE-I4B SCC - 2017.05.17 (Sawada.Y)
  Seabas2VC707_part1_20170517.xpr.zip

Tips

• Text on FPGA training
  • prepapration: OFTC_preparation.pdf

  • main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf

  • training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
  • reference: OFTC_ref_note.pdf, references.pdf
• Useful links
  • Qiita
  • Electrical Engineering
  • SiTCP User Community
  • Takeuchi's memo for electric circuit

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

FE-I4 Readout Test

• Firmware for VC707 to readout FE-I4B SCC - 2017.05.17 (Sawada.Y)
  Seabas2VC707_part1_20170517.xpr.zip

Comments

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

Comments

<--/commentPlugin-->

RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

Ryo Nagai - 2016-10-17

Comments

<--/commentPlugin-->

RD53A DAQ Development

Comments

RD53A DAQ Development

Article text.

-- Atlasj Silicon - 2016-10-11

Comments

<--/commentPlugin-->