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RD53A DAQ Development
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FE-I4 Readout Test |
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- FPGA Hardware and Additional apparatuses
- FPGA Hardware
- Prerequisites
Target devices : Virtex-7 VC707 Evaluation Platform (xc7vx485tffg1761-2) Tool Version : Xilinx Vivado 2015.4 or later tools If you are using Kintex-7 KC705 Evaluation Platform, you need to change the SiTCP module in the firmware to XC7KSiTCPlib32k.
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- source : trunk/multi_chip_FEI4/Software_SEABAS2
- SiTCP IP Address : Default (192.168.10.16)
- How to config FEI4
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- For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
Please refer to SEABAS2 DAQ Usages.
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- For example, execute on your terminal run 1 0111 which is a command to do "Digital Injection and mask chip_1 to chip3."
Please refer to SEABAS2 DAQ Usages.
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- Release
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- Notes
- When you use the original conversion board, you need to change the pin assignment to comply with your board.
(Default firmware is build for a setup of Osaka Univ.)
- Already-known warnings
- Redundant IBUF can be ignored. "Could not create 'IBUF_LOW_PWR' constraint because ..." and "Removing redundant IBUF since ..." can be ignored.
- Unused registers.
- Programming VC707 Virtex7 BPI Flash memory
- Generate a bitstream (.bit) file in the normal way.
- Run this TCL command inside Vivado:
$ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 /path/to/bitfile.bit" -file mynewmcs.mcs
- Open Vivado Lab Edition
- Open Hardware Manager, open target board
- Tools > Add Configuration Memory Device
- Select this part:
Name: mt28gu01gaax1e-bpi-x16 Part: mt28gu01gaax1e Manufacturer: Micron Alias: 28f00ag18f Family: g18 Type: bpi Density: 1024 Width: x16
- Click OK to "Do you want to program the configuration memory device now?"
- Add your .mcs file to the Configuration File field
- Hit OK
- Right click on device >> Boot from Configuration Memory Device
- Change the VC707 FPGA Board Configuration Mode JTAG to Master BPI. Set SW13 DIP switch M[2:0]=010.
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