Difference: RD53ADAQdevelopment (10 vs. 11)

Revision 112017-06-25 - AtlasjSilicon

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RD53A DAQ Development

Introduction

RD53 is a prospective ASIC for the HL-LHC upgrade.

Deleted:

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/opt/Xilinx/Vivado/2016.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

-- Ryo Nagai - 2016-10-17

FE-I4 Readout Test

Changed:

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Firmware for VC707 to readout FE-I4B SCC - 2017.06.12 (Sawada.Y)
- Seabas2VC707_part1_20170612.xpr.zip - SiTCP <-> SIO_REG was modified.
- Seabas2VC707_part1_20170613.xpr.zip
- Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.

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Firmware for VC707 to readout FE-I4B SCC - 2017.06.12 (Sawada.Y)
- Seabas2VC707_part1_20170612.xpr.zip - SiTCP <-> SIO_REG was modified.
- Seabas2VC707_part1_20170613.xpr.zip
- Seabas2VC707_part1_20170615.xpr.zip - corrected to output RunMode command signal.

Added:

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注意点(日本語暫定簡易版)
1.VC707用のものなのでKC705を利用の際は、SiTCPのGMIIとSGMIIの変換部分は編集する必要があります。
2.FMC LPCのピン配置は阪大で使用しているテスト用変換基板のピン配置に準拠しています。それ以外の変換基板を利用の際は制約ファイルを編集してピン配置を変更する必要があります。
3.現在、論理合成時のエラーは既知のものです。無視して構いません。気になる方は修正をお願いします。
4.インプリメンテーション時にタイミング違反の警告メッセージが出ますが無視してください。
5.FEI4B SCCにConfigが通ることまで確認しています。FEI4からの受信データをPCへTCPで転送できているかどうかは6/25時点でまだ未確認です(澤田)。
6.検証時、DAQソフトウェアは SEABAS2用のものをご利用ください。
SiTCP IP Address : Default(192.168.10.16)
source : trunk/multi_chip_FEI4/Software_SEABAS2

SLVS <-> LVDS level shiter designed by Ryo Nagai: LVDS2SLVS_Pins.zip

Tips

Text on FPGA training
- prepapration: OFTC_preparation.pdf
- main body: OFTC_0.pdf, OFTC_1.pdf, OFTC_2_1.pdf, OFTC_2_2.pdf, OFTC_2_3.pdf, OFTC_2_4.pdf, OFTC_3.pdf, OFTC_4_1.pdf, OFTC_4_2.pdf, OFTC_4_3.pdf, OFTC_5.pdf, OFTC_6.pdf, OFTC_7.pdf, OFTC_8.pdf, OFTC_9.pdf
- training course: OFTC_lab_c1_rev20.pdf, OFTC_lab_s1_rev20.pdf, OFTC_lab_i1_rev11.pdf, OFTC_lab_i2_rev13.pdf
- reference: OFTC_ref_note.pdf, references.pdf
Useful links

Comments

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