Difference: FE65p2ChipDAQ (1 vs. 30)

Revision 302017-12-08 - KojiNakamura

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

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  KEKFE65-13@-20degC

CompVbnDac: 50
PrempVbpDac: 120
VbnLccDac : 200
VffDac : 15
Added:
>
>

XpressK7 DAQ

FE65byXpressK7

 

Images


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DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
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DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
DSC_1505  DSC_1509  DSC_1510  IMG_1573 
IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
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PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
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Revision 292017-10-17 - AtlasjSilicon

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 36 to 36
 
KEKFE65-14 PT (type3)   Prmp200   pixel size 50*50
KEKFE65-15 PT no space (type10)   Prmp200   pixel size 50*50
leakage increase roughly in proportion to HV
KEKFE65-16 no bias (type8)   Prmp200   pixel size 25*100
Changed:
<
<
>
>
KEKFE65-17          
KEKFE65-18          
KEKFE65-19          
KEKFE65-20          
 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
  • Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35

Revision 282017-07-05 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 101 to 101
  https://eutelescope.web.cern.ch/forum/multiple-dut-events-tlu-trigger
Changed:
<
<
instructions on eudaq -> http://yarr.readthedocs.io/en/latest/eudaq.html
>
>
instructions on eudaq -> http://yarr.readthedocs.io/en/latest/eudaq.html

Exttrigger mode

Seabas firmware :
MPPC bias : ~60V
Latency : 70

///// memo

KEKFE65-13@-20degC

CompVbnDac: 50
PrempVbpDac: 120
VbnLccDac : 200
VffDac : 15

 

Images


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DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
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DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
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IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
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Revision 272017-06-17 - JunkiSuzuki

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DAQ development for FE65-P2 chip

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KEKFE65-11 poly-Si (type8)   unknown 3e15 External voltage(digital 1.2V, analog 1.2V) is necessary.
KEKFE65-12 poly-Si (type2)   Prmp150   pixel size 50*50
KEKFE65-13 no bias (type5)   Prmp150   pixel size 50*50
Changed:
<
<
KEKFE65-14 PT (type3)   Prmp100   pixel size 50*50
>
>
KEKFE65-14 PT (type3)   Prmp200   pixel size 50*50
 
KEKFE65-15 PT no space (type10)   Prmp200   pixel size 50*50
leakage increase roughly in proportion to HV
KEKFE65-16 no bias (type8)   Prmp200   pixel size 25*100

Revision 262017-06-17 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

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KEKFE65-6 no bias structure   no 3e15  
KEKFE65-7 no bias structure no hit (digitalscan)      
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15
preampvbp->250 ::: good
Changed:
<
<
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  
>
>
KEKFE65-9 poly-Si (type1)   compVBAndaq,
priampVbnFolDac
3e15  
 
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 3e15 patch work...1,2,4,7 (Vthin1 80, Vthin2 60)
KEKFE65-11 poly-Si (type8)   unknown 3e15 External voltage(digital 1.2V, analog 1.2V) is necessary.
KEKFE65-12 poly-Si (type2)   Prmp150   pixel size 50*50
KEKFE65-13 no bias (type5)   Prmp150   pixel size 50*50
KEKFE65-14 PT (type3)   Prmp100   pixel size 50*50
Changed:
<
<
KEKFE65-15 PT no space (type10)   Prmp200   pixel size 50*50
>
>
KEKFE65-15 PT no space (type10)   Prmp200   pixel size 50*50
leakage increase roughly in proportion to HV
 
KEKFE65-16 no bias (type8)   Prmp200   pixel size 25*100

DAQ development by SPEC

Revision 252017-06-16 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 27 to 27
 
KEKFE65-5          
KEKFE65-6 no bias structure   no 3e15  
KEKFE65-7 no bias structure no hit (digitalscan)      
Changed:
<
<
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15

preampvbp->250 ::: good
>
>
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15
preampvbp->250 ::: good
 
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 3e15 patch work...1,2,4,7 (Vthin1 80, Vthin2 60)
KEKFE65-11 poly-Si (type8)   unknown 3e15 External voltage(digital 1.2V, analog 1.2V) is necessary.
Added:
>
>
KEKFE65-12 poly-Si (type2)   Prmp150   pixel size 50*50
KEKFE65-13 no bias (type5)   Prmp150   pixel size 50*50
KEKFE65-14 PT (type3)   Prmp100   pixel size 50*50
KEKFE65-15 PT no space (type10)   Prmp200   pixel size 50*50
KEKFE65-16 no bias (type8)   Prmp200   pixel size 25*100
 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch

Revision 242017-02-22 - AtlasjSilicon

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 29 to 29
 
KEKFE65-7 no bias structure no hit (digitalscan)      
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15

preampvbp->250 ::: good
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  
Changed:
<
<
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 0 patch work...1,2,4,7 (Vthin1 80, Vthin2 60)
KEKFE65-11 poly-Si (type8)   unknown 0 External voltage(digital 1.2V, analog 1.2V) is necessary.
>
>
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 3e15 patch work...1,2,4,7 (Vthin1 80, Vthin2 60)
KEKFE65-11 poly-Si (type8)   unknown 3e15 External voltage(digital 1.2V, analog 1.2V) is necessary.
 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
Line: 95 to 95
 

https://eutelescope.web.cern.ch/forum/multiple-dut-events-tlu-trigger

Added:
>
>
instructions on eudaq -> http://yarr.readthedocs.io/en/latest/eudaq.html
 

Images


DSC_1418.JPG DSC_1420.JPG DSC_1421.JPG DSC_1423.JPG
DSC_1418  DSC_1420  DSC_1421  DSC_1423 
DSC_1424.JPG DSC_1425.JPG DSC_1426.JPG DSC_1434.JPG
DSC_1424  DSC_1425  DSC_1426  DSC_1434 
DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
DSC_1459  DSC_1464  DSC_1466  DSC_1467 
DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
DSC_1505  DSC_1509  DSC_1510  IMG_1573 
IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
There are 24 images in this page

Revision 232017-02-17 - AtlasjSilicon

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 29 to 29
 
KEKFE65-7 no bias structure no hit (digitalscan)      
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15

preampvbp->250 ::: good
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  
Changed:
<
<
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 0  
KEKFE65-11 poly-Si (type8)   unknown 0  
>
>
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 0 patch work...1,2,4,7 (Vthin1 80, Vthin2 60)
KEKFE65-11 poly-Si (type8)   unknown 0 External voltage(digital 1.2V, analog 1.2V) is necessary.
 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch

Revision 222017-02-17 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 29 to 29
 
KEKFE65-7 no bias structure no hit (digitalscan)      
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15

preampvbp->250 ::: good
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  
Changed:
<
<


>
>
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 0  
KEKFE65-11 poly-Si (type8)   unknown 0  

 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
  • Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35

Revision 212017-02-04 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 14 to 14
 Timon's talk in AUW April 2016

Timon's Twiki

Added:
>
>
FE65-P2.pdf
 

Chips and Bump Bonding at SLAC


sensor name,bias(type), condition, patch work, dose,

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META FILEATTACHMENT attachment="IMG_1574.JPG" attr="" comment="" date="1467040073" name="IMG_1574.JPG" path="IMG_1574.JPG" size="1219002" user="KojiNakamura" version="1"
META FILEATTACHMENT attachment="IMG_1575.JPG" attr="" comment="" date="1467040073" name="IMG_1575.JPG" path="IMG_1575.JPG" size="1460518" user="KojiNakamura" version="1"
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Added:
>
>
META FILEATTACHMENT attachment="FE65-P2.pdf" attr="" comment="" date="1486182666" name="FE65-P2.pdf" path="FE65-P2.pdf" size="3430048" user="JunkiSuzuki" version="1"

Revision 202017-02-03 - JunkiSuzuki

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DAQ development for FE65-P2 chip

Line: 25 to 25
 
KEKFE65-5          
KEKFE65-6 no bias structure   no 3e15  
KEKFE65-7 no bias structure no hit (digitalscan)      
Changed:
<
<
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15
>
>
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15

preampvbp->250 ::: good
 
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  


DAQ development by SPEC

Revision 192017-02-03 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 25 to 25
 
KEKFE65-5          
KEKFE65-6 no bias structure   no 3e15  
KEKFE65-7 no bias structure no hit (digitalscan)      
Changed:
<
<
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15  
>
>
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15
 
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  


DAQ development by SPEC

Revision 182016-10-26 - KojiNakamura

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 71 to 71
 

HitOr self trigger scan

1. Run digital scan
2. Run analog scan
3. Prepare config:
- Enable all pixels: # bin/config_fe65-p2 fe65p2.json (Overwrites config file)
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_digitalscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
- Apply analog scan mask: # bin/applyMask fe65p2_ch0_analogscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
4. Run noise scan (~5min)
5. Apply noise mask:
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_noisescan_NoiseMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
6. Mask stuck/noise hitter pixels:
- #bin/fixHitbus fe65p2.json (takes quite some time ~15min)
- Only pixels which will get masked get printed to stdout, optimally these should not be many
- If many pixels appear to not work something is wrong
- You can observe the process by probing HitOr Output and Trigger, there should be two hitOr pulses per trigger
- The program produces a mask hitbus_enMask.png
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
7. Run exttrigger scan:
- If everything went right you should observe a trigger rate of a few Hz without a particle source
- With source the rate should be much higher
- The internal dead time is 200bc (currently hardcoded for testing)

Added:
>
>

YARR DAQ in EUDAQ

Hi Koji,

See here for instructions on eudaq: http://yarr.readthedocs.io/en/eudaq/eudaq.html
Swap into branch ďeudaqĒ. Donít forget to program the correct firmware (assuming you already have the adapter board).

Some remarks:
- I had a merge conflict problem in the firmware and Iím not 100% that is resolvers properly. If it is not right, YARR would not answer to triggers, which you should see if the RC does not see more trigger.
- I had to change the way events get send to the RC, this is untested and I hope it works.
- There is a version of the converter, but Iím sure there were local changes and I canít get onto the eudaq machine at SLAC due to some stupid permissions. We need to wait until someone sends me the file. 

If you give me a not to random time window in your night where I can test some things with, we could do that. I have to run some errants and will not be at my laptop the whole time.

Otherwise we can get everything running once Iím there in person.

Cheers,
Timon

https://eutelescope.web.cern.ch/forum/multiple-dut-events-tlu-trigger

 

Images


DSC_1418.JPG DSC_1420.JPG DSC_1421.JPG DSC_1423.JPG
DSC_1418  DSC_1420  DSC_1421  DSC_1423 
DSC_1424.JPG DSC_1425.JPG DSC_1426.JPG DSC_1434.JPG
DSC_1424  DSC_1425  DSC_1426  DSC_1434 
DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
DSC_1459  DSC_1464  DSC_1466  DSC_1467 
DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
DSC_1505  DSC_1509  DSC_1510  IMG_1573 
IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
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Revision 172016-10-20 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Revision 162016-10-19 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

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DSC_1418.JPG DSC_1420.JPG DSC_1421.JPG DSC_1423.JPG
DSC_1418  DSC_1420  DSC_1421  DSC_1423 
DSC_1424.JPG DSC_1425.JPG DSC_1426.JPG DSC_1434.JPG
DSC_1424  DSC_1425  DSC_1426  DSC_1434 
DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
DSC_1459  DSC_1464  DSC_1466  DSC_1467 
DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
DSC_1505  DSC_1509  DSC_1510  IMG_1573 
IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
There are 24 images in this page

-- Koji Nakamura - 2016-04-21

Added:
>
>

Log note

AfterIrrad20161018

 
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META FILEATTACHMENT attachment="DSC_1420.JPG" attr="" comment="" date="1464080312" name="DSC_1420.JPG" path="DSC_1420.JPG" size="3171470" user="KojiNakamura" version="1"

Revision 152016-10-18 - JunkiSuzuki

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

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How to configure chips and run scan

tuning

  1. source gcc4.8.2
    source /opt/rh/devtool/set_2/enable
Changed:
<
<
  1. write FPGA
    ./bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
>
>
  1. write FPGA
    cd /home/atlasj/work/SPEC/Yarr/src
    ./bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
 
  1. Delete fe65p2.json
    cd ~/work/SPEC/Yarr/src
    rm -f fe65p2.json
  2. Digital scan
    ./primlist/scan.sh digitalscan <KEKFE65-(module #)_th(threshold)>

Revision 142016-10-13 - AtlasjSilicon

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DAQ development for FE65-P2 chip

Line: 47 to 47
 sudo depmod cd ../ ; make
Changed:
<
<
  • install driver and program firmware to the SPEC card FPGA
    sudo rmmod specDriver
>
>
  • install driver and program firmware to the SPEC card FPGAsudo rmmod specDriver
 
sudo modprobe  specDriver
bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
bin/test

Revision 132016-10-07 - AtlasjSilicon

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DAQ development for FE65-P2 chip

Line: 24 to 24
 
KEKFE65-4          
KEKFE65-5          
KEKFE65-6 no bias structure   no 3e15  
Changed:
<
<
KEKFE65-7 no bias structure        
KEKFE65-8 poly-Si (type2) 右上が剥がれている no 3e15  
>
>
KEKFE65-7 no bias structure no hit (digitalscan)      
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15  
 
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  


DAQ development by SPEC

Revision 122016-10-06 - AtlasjSilicon

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DAQ development for FE65-P2 chip

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KEKFE65-3          
KEKFE65-4          
KEKFE65-5          
Changed:
<
<
KEKFE65-6 no bias srtructure   no 3e15  
KEKFE65-7          
KEKFE65-8       3e15  
KEKFE65-9     compVBAndaq, priampVbnFolDac 3e15  
>
>
KEKFE65-6 no bias structure   no 3e15  
KEKFE65-7 no bias structure        
KEKFE65-8 poly-Si (type2) 右上が剥がれている no 3e15  
KEKFE65-9 poly-Si (type1)   compVBAndaq, priampVbnFolDac 3e15  
 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
Line: 57 to 57
 

How to configure chips and run scan

tuning

  1. source gcc4.8.2
    source /opt/rh/devtool/set_2/enable
Added:
>
>
  1. write FPGA
    ./bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
 
  1. Delete fe65p2.json
    cd ~/work/SPEC/Yarr/src
    rm -f fe65p2.json
  2. Digital scan
    ./primlist/scan.sh digitalscan <KEKFE65-(module #)_th(threshold)>

Revision 112016-10-06 - JunkiSuzuki

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DAQ development for FE65-P2 chip

Line: 16 to 16
 Timon's Twiki

Chips and Bump Bonding at SLAC

Changed:
<
<
KEKFE1

KEKFE2

KEKFE3

KEKFE4

KEKFE5

KEKFE6

>
>

sensor name,bias(type), condition, patch work, dose,
name bias structure(type) condition patch work dose comment
KEKFE65-1          
KEKFE65-2          
KEKFE65-3          
KEKFE65-4          
KEKFE65-5          
KEKFE65-6 no bias srtructure   no 3e15  
KEKFE65-7          
KEKFE65-8       3e15  
KEKFE65-9     compVBAndaq, priampVbnFolDac 3e15  


 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
  • Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35

Revision 102016-10-03 - JunkiSuzuki

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DAQ development for FE65-P2 chip

Changed:
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<
>
>

 

Introduction

FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the RD53A/B chips used by HL-LHC ITK pixel upgrade.

Line: 54 to 54
  bin/benchmarkDma

How to configure chips and run scan

Added:
>
>

tuning

  1. source gcc4.8.2
    source /opt/rh/devtool/set_2/enable
  2. Delete fe65p2.json
    cd ~/work/SPEC/Yarr/src
    rm -f fe65p2.json
  3. Digital scan
    ./primlist/scan.sh digitalscan <KEKFE65-(module #)_th(threshold)>
  4. Analog scan
    ./primlist/scan.sh analogscan <KEKFE65-(module #)_th(threshold)>
  5. Threshold scan
    ./primlist/scan.sh thresholdscan <KEKFE65-(module #)_th(threshold)>
  6. Grobal tuning
    change Vthin1 and Vthin2 (fe65p2.json)
    differential threshold: threshold=Vthin1-Vthin2 ※Vthin2>25

  7. set thresold tuning target
    edit Line147 in scanconsole65.cpp
    bookiie.setTargetThreshold(threshold) 
  8. Local tuning
    ./primlist/scan.sh tune_pixelthreshold <KEKFE65-(module #)_th(threshold)>
 

General scan consol

HitOr self trigger scan

Line: 61 to 71
 1. Run digital scan
2. Run analog scan
3. Prepare config:
- Enable all pixels: # bin/config_fe65-p2 fe65p2.json (Overwrites config file)
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_digitalscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
- Apply analog scan mask: # bin/applyMask fe65p2_ch0_analogscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
4. Run noise scan (~5min)
5. Apply noise mask:
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_noisescan_NoiseMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
6. Mask stuck/noise hitter pixels:
- #bin/fixHitbus fe65p2.json (takes quite some time ~15min)
- Only pixels which will get masked get printed to stdout, optimally these should not be many
- If many pixels appear to not work something is wrong
- You can observe the process by probing HitOr Output and Trigger, there should be two hitOr pulses per trigger
- The program produces a mask hitbus_enMask.png
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
7. Run exttrigger scan:
- If everything went right you should observe a trigger rate of a few Hz without a particle source
- With source the rate should be much higher
- The internal dead time is 200bc (currently hardcoded for testing)

Images

Changed:
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IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
There are 24 images in this page
>
>

DSC_1418.JPG DSC_1420.JPG DSC_1421.JPG DSC_1423.JPG
DSC_1418  DSC_1420  DSC_1421  DSC_1423 
DSC_1424.JPG DSC_1425.JPG DSC_1426.JPG DSC_1434.JPG
DSC_1424  DSC_1425  DSC_1426  DSC_1434 
DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
DSC_1459  DSC_1464  DSC_1466  DSC_1467 
DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
DSC_1505  DSC_1509  DSC_1510  IMG_1573 
IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
There are 24 images in this page
  -- Koji Nakamura - 2016-04-21

Revision 92016-08-23 - KojiNakamura

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Introduction

Changed:
<
<
FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the RD53A /B chips used by HL-LHC ITK pixel upgrade.
>
>
FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the RD53A/B chips used by HL-LHC ITK pixel upgrade.
  more information is available in :
Line: 14 to 14
 Timon's talk in AUW April 2016

Timon's Twiki

Changed:
<
<

Bump Bonding at SLAC

>
>

Chips and Bump Bonding at SLAC

KEKFE1

KEKFE2

KEKFE3

KEKFE4

KEKFE5

KEKFE6

 

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
  • Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35
Changed:
<
<

How to setup SPEC board

>
>

How to setup SPEC board

 
  • on SLC6 or CentOS7
    • need devtoolset-2 for gcc48
  • install font for gnuplot
    sudo yum -y install xorg-x11-fonts-ISO8859*
Line: 41 to 53
 

bin/benchmarkDma

Added:
>
>

How to configure chips and run scan

General scan consol

HitOr self trigger scan

1. Run digital scan
2. Run analog scan
3. Prepare config:
- Enable all pixels: # bin/config_fe65-p2 fe65p2.json (Overwrites config file)
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_digitalscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
- Apply analog scan mask: # bin/applyMask fe65p2_ch0_analogscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
4. Run noise scan (~5min)
5. Apply noise mask:
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_noisescan_NoiseMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
6. Mask stuck/noise hitter pixels:
- #bin/fixHitbus fe65p2.json (takes quite some time ~15min)
- Only pixels which will get masked get printed to stdout, optimally these should not be many
- If many pixels appear to not work something is wrong
- You can observe the process by probing HitOr Output and Trigger, there should be two hitOr pulses per trigger
- The program produces a mask hitbus_enMask.png
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
7. Run exttrigger scan:
- If everything went right you should observe a trigger rate of a few Hz without a particle source
- With source the rate should be much higher
- The internal dead time is 200bc (currently hardcoded for testing)

 

Images

DSC_1418.JPG DSC_1420.JPG DSC_1421.JPG DSC_1423.JPG
DSC_1418  DSC_1420  DSC_1421  DSC_1423 
DSC_1424.JPG DSC_1425.JPG DSC_1426.JPG DSC_1434.JPG
DSC_1424  DSC_1425  DSC_1426  DSC_1434 
DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
DSC_1459  DSC_1464  DSC_1466  DSC_1467 
DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
DSC_1505  DSC_1509  DSC_1510  IMG_1573 
IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
There are 24 images in this page

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Revision 72016-06-25 - KojiNakamura

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DAQ development for FE65-P2 chip

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DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
  • Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35
Added:
>
>

How to setup SPEC board

  • on SLC6 or CentOS7
    • need devtoolset-2 for gcc48
  • install font for gnuplot
    sudo yum -y install xorg-x11-fonts-ISO8859*
  • install software and firmware from git
mkdir -p /home/atlasj/work/SPEC/YARR 
cd /home/atlasj/work/SPEC/YARR/
git clone https://github.com/Yarr/Yarr.git
git fetch
git checkout fe65_p2
cd /home/atlasj/work/SPEC/YARR/Yarr/src/kernel
make
sudo make install
sudo depmod
cd ../ ; make

  • install driver and program firmware to the SPEC card FPGA
    sudo rmmod specDriver
sudo modprobe  specDriver
bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
bin/test
 
Added:
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>
bin/benchmarkDma
 

Images

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PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
There are 24 images in this page
  -- Koji Nakamura - 2016-04-21

Revision 62016-06-05 - KojiNakamura

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DAQ development for FE65-P2 chip

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Revision 32016-05-24 - KojiNakamura

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DAQ development for FE65-P2 chip

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  • Installed CERN CentOS7 to pcatutt21.cern.ch
  • Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35
Added:
>
>

Images

DSC_1418.JPG DSC_1420.JPG DSC_1421.JPG DSC_1423.JPG
DSC_1418  DSC_1420  DSC_1421  DSC_1423 
DSC_1424.JPG DSC_1425.JPG DSC_1426.JPG DSC_1434.JPG
DSC_1424  DSC_1425  DSC_1426  DSC_1434 
DSC_1459.JPG DSC_1464.JPG DSC_1466.JPG DSC_1467.JPG
DSC_1459  DSC_1464  DSC_1466  DSC_1467 
DSC_1505.JPG DSC_1509.JPG DSC_1510.JPG IMG_1573.JPG
DSC_1505  DSC_1509  DSC_1510  IMG_1573 
IMG_1574.JPG IMG_1575.JPG IMG_1576.JPG PL21_bottom.jpg
IMG_1574  IMG_1575  IMG_1576  PL21_bottom 
PL21_bottom_middle.jpg PL51_bottom.jpg PL51_bottom_middle.jpg PL51_bottom_right.jpg
PL21_bottom_middle  PL51_bottom  PL51_bottom_middle  PL51_bottom_right 
There are 24 images in this page
 -- Koji Nakamura - 2016-04-21 \ No newline at end of file
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Revision 22016-05-19 - KojiNakamura

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META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Line: 17 to 17
 

Bump Bonding at SLAC

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
Changed:
<
<
>
>
  • Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35
  -- Koji Nakamura - 2016-04-21

Revision 12016-04-21 - KojiNakamura

Line: 1 to 1
Added:
>
>
META TOPICPARENT name="WebHome"

DAQ development for FE65-P2 chip

Introduction

FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the RD53A /B chips used by HL-LHC ITK pixel upgrade.

more information is available in :

motivation talk in AUW April 2016

Timon's talk in AUW April 2016

Timon's Twiki

Bump Bonding at SLAC

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch

-- Koji Nakamura - 2016-04-21

 
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