DAQ development for FE65-P2 chip
Introduction
FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the RD53A/B chips used by HL-LHC ITK pixel upgrade.
more information is available in :
motivation talk in AUW April 2016
Timon's talk in AUW April 2016
Timon's Twiki
Chips and Bump Bonding at SLAC
sensor name,bias(type), condition, patch work, dose,
name |
bias structure(type) |
condition |
patch work |
dose |
comment |
KEKFE65-1 |
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KEKFE65-2 |
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KEKFE65-3 |
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KEKFE65-4 |
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KEKFE65-5 |
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KEKFE65-6 |
no bias structure |
|
no |
3e15 |
|
KEKFE65-7 |
no bias structure |
no hit (digitalscan) |
|
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KEKFE65-8 |
poly-Si (type2) |
missing bumpbonds at right top corner |
no |
3e15 |
|
KEKFE65-9 |
poly-Si (type1) |
|
compVBAndaq, priampVbnFolDac |
3e15 |
|
DAQ development by SPEC
- Installed CERN CentOS7 to pcatutt21.cern.ch
- Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35
How to setup SPEC board
mkdir -p /home/atlasj/work/SPEC/YARR
cd /home/atlasj/work/SPEC/YARR/
git clone https://github.com/Yarr/Yarr.git
git fetch
git checkout fe65_p2
cd /home/atlasj/work/SPEC/YARR/Yarr/src/kernel
make
sudo make install
sudo depmod
cd ../ ; make
- install driver and program firmware to the SPEC card FPGA
sudo rmmod specDriver
sudo modprobe specDriver
bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
bin/test
bin/benchmarkDma
How to configure chips and run scan
tuning
- source gcc4.8.2
source /opt/rh/devtool/set_2/enable
- write FPGA
./bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
- Delete fe65p2.json
cd ~/work/SPEC/Yarr/src
rm -f fe65p2.json
- Digital scan
./primlist/scan.sh digitalscan <KEKFE65-(module #)_th(threshold)>
- Analog scan
./primlist/scan.sh analogscan <KEKFE65-(module #)_th(threshold)>
- Threshold scan
./primlist/scan.sh thresholdscan <KEKFE65-(module #)_th(threshold)>
- Grobal tuning
change Vthin1 and Vthin2 (fe65p2.json)
differential threshold: threshold=Vthin1-Vthin2 ※Vthin2>25
- set thresold tuning target
edit Line147 in scanconsole65.cpp bookiie.setTargetThreshold(threshold)
- Local tuning
./primlist/scan.sh tune_pixelthreshold <KEKFE65-(module #)_th(threshold)>
General scan consol
HitOr self trigger scan
1. Run digital scan
2. Run analog scan
3. Prepare config:
- Enable all pixels: # bin/config_fe65-p2 fe65p2.json (Overwrites config file)
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_digitalscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
- Apply analog scan mask: # bin/applyMask fe65p2_ch0_analogscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
4. Run noise scan (~5min)
5. Apply noise mask:
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_noisescan_NoiseMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
6. Mask stuck/noise hitter pixels:
- #bin/fixHitbus fe65p2.json (takes quite some time ~15min)
- Only pixels which will get masked get printed to stdout, optimally these should not be many
- If many pixels appear to not work something is wrong
- You can observe the process by probing
HitOr Output and Trigger, there should be two hitOr pulses per trigger
- The program produces a mask hitbus_enMask.png
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
7. Run exttrigger scan:
- If everything went right you should observe a trigger rate of a few Hz without a particle source
- With source the rate should be much higher
- The internal dead time is 200bc (currently hardcoded for testing)
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IMG_1573 |
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IMG_1574 |
IMG_1575 |
IMG_1576 |
PL21_bottom |
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PL21_bottom_middle |
PL51_bottom |
PL51_bottom_middle |
PL51_bottom_right |
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--
Koji Nakamura - 2016-04-21