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TLUfirmware


TLUadapter board

設計ミスでSEABASのJ1とJ3どちらか片方にしか接続できない問題(新しいものでは解決済み)

Kyocera connector側：NIMinが回路図と反対側に繋がっていた->不幸なことにJ3 connectorであり、SEABASの接続先がADCだった(FPGAとは繋がっていなかった)

Integration testではJ3に接続するつもりだったconnectorをSEABAS側J2に接続する

SEABASのFPGAではLVDS信号は扱えない？

  silk in/out signal J2 PIN
NIMin4   in NIM D79 N2
NIMin5   in NIM D78 N1
NIMin6   in NIM D77 P1
NIMin7   in NIM D76 P3
NIMout2 NIMout3 out NIM D74 P5
NIMout3 NIMout2 out NIM D75 P4
NIMout4 NIMout? out NIM D72 R2
NIMout5 NIMout4 out NIM D73 R1
dout0_p MPPC0 in (LVDS) D52 L3
dout0_n in (LVDS) D53 L2
dout_cmos0 in (TTL) D54 M5
DAC_LDACn0 out   D55 M4
dout1_p MPPC1 in (LVDS) D44 J3
dout1_n in (LVDS) D45 J1
dout_cmos1 in (TTL) D46 K5
DAC_LDACn1 out   D47 K3
DAC_PREn1 out   D48 K2
DAC_FS1 out   D49 K1
DAC_DIN1 out   D50 L5
DAC_SCLK1 out   D51 L4
dout2_p MPPC2 in (LVDS) D63 U4
dout2_n in (LVDS) D62 U5
dout_cmos2 in (TTL) D61 V1
DAC_LDACn2 out   D60 V2
DAC_PREn2 out   D40 H2
DAC_FS2 out   D41 H1
DAC_DIN2 out   D42 J5
DAC_SCLK2 out   D43 J4
dout3_p MPPC3 in (LVDS) D71 R3
dout3_n in (LVDS) D70 R5
dout_cmos3 in (TTL) D69 T2
DAC_LDACn3 out   D68 T3
DAC_PREn3 out   D67 T4
DAC_FS3 out   D66 T5
DAC_DIN3 out   D65 U1
DAC_SCLK3 out   D64 U2

DAC firmware

-- Atlasj Silicon - 2018-01-31

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PDFpdf 110520seabas2a.pdf r1 manage 454.4 K 2018-01-31 - 06:14 AtlasjSilicon  
PDFpdf tlv5630.pdf r1 manage 1155.8 K 2018-01-31 - 06:14 AtlasjSilicon  
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Topic revision: r2 - 2018-01-31 - AtlasjSilicon
 
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