Difference:
TLUfirmware
(22 vs. 23)
Revision 23
2018-03-02 -
AtlasjSilicon
Line: 1 to 1
META TOPICPARENT
name="FermilabTestbeam2018"
TLUfirmware
Line: 62 to 62
ADC_P14
LVCMOSin[0]
CMOSin6
in
D56
M2
special connection for CMOSin
HSIO2 busy
ADC_N14
LVCMOSout[0]
CMOSout0
out
D57
M1
special connection for CMOSout
HSIO2 exttrigger
Changed:
<
<
本番用
>
>
本番用(3/1更新)
接続
信号名
silk
in/out
J1
FPGA
comments
信号名
信号名
silk
in/out
J3
FPGA
comments
CMOSin0
LVCMOSin[0]
in
D0
E10
HSIO2 busy
NIMin4
NIMin[4]
in
D96
AB4
ROI
Changed:
<
<
CMOSin1
LVCMOSin[1]
in
D1
A8
Pico Gen()
NIMin5
NIMin[5]
in
D97
AB5
SVX busy
>
>
CMOSin1
LVCMOSin[1]
in
D1
A8
Pico Gen(no signal)
NIMin5
NIMin[5]
in
D97
AB5
SVX busy
CMOSin2
LVCMOSin[2]
in
D2
C8
NIMin6
NIMin[6]
in
D98
AC1
DRS4 busy
CMOSin3
LVCMOSin[3]
in
D3
D8
NIMin7
NIMin[7]
in
D99
AC2
CMOSin4
LVCMOSin[4]
in
D4
A7
NIMout2
NIMout[2]
out
D115
AC3
NIMin[4]
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