Difference: TLUfirmware (21 vs. 22)

Revision 222018-03-01 - AtlasjSilicon

Line: 1 to 1
 
META TOPICPARENT name="FermilabTestbeam2018"

TLUfirmware

Line: 65 to 65
 本番用
接続 信号名 silk in/out J1 FPGA comments     信号名 信号名 silk in/out J3 FPGA comments
CMOSin0 LVCMOSin[0]   in D0 E10 HSIO2 busy     NIMin4 NIMin[4]   in D96 AB4 ROI
Changed:
<
<
CMOSin1 LVCMOSin[1]   in D1 A8       NIMin5 NIMin[5]   in D97 AB5 SVX busy
CMOSin2 LVCMOSin[2]   in D2 C8       NIMin6 NIMin[6]   in D98 AC1  
>
>
CMOSin1 LVCMOSin[1]   in D1 A8 Pico Gen()     NIMin5 NIMin[5]   in D97 AB5 SVX busy
CMOSin2 LVCMOSin[2]   in D2 C8       NIMin6 NIMin[6]   in D98 AC1 DRS4 busy
 
CMOSin3 LVCMOSin[3]   in D3 D8       NIMin7 NIMin[7]   in D99 AC2  
CMOSin4 LVCMOSin[4]   in D4 A7       NIMout2 NIMout[2]   out D115 AC3 NIMin[4]
CMOSin5 LVCMOSin[5]   in D5 B7       NIMout3 NIMout[3]   out D114 AC4 LGAD trigger(TrigBeam)
CMOSin6 LVCMOSin[6]   in D6 C7       NIMout4 NIMout[4]   out D113 AD1 SVX4 timestamp CLK100K
CMOSout0 LVCMOSout[0]   out D7 B6 NIMin[5]     NIMout5 NIMout[5]   out D112 AD3 SVX4 trigger(TrigBeam)
CMOSout1 LVCMOSout[1]   out D8 C6 busy OR     dout0 dout[0] MPPCctl1 in D92 AA4  
Changed:
<
<
CMOSout2 LVCMOSout[2]   out D9 D6 Pico ext(TrigBeam)     dout_cmos0   in D94 AB1  
CMOSout3 LVCMOSout[3]   out D10 A5 TrigBeam     DAC_LDACn0   out D95 AB2  
>
>
CMOSout2 LVCMOSout[2]   out D9 D6 Pico Ext(TrigBeam)     dout_cmos0   in D94 AB1  
CMOSout3 LVCMOSout[3]   out D10 A5 Pico D(TrigBeam)     DAC_LDACn0   out D95 AB2  
 
CMOSout4 LVCMOSout[4]   out D11 B5 TrigBeam     dout1 dout[1] MPPCctl2 in D84 W4  
CMOSout5 LVCMOSout[5]   out D12 D5 TrigBeam     dout_cmos1   in D85 W5  
CMOSout6 LVCMOSout[6]   out D13 A4 busy OR     DAC_LDACn1   out D87 Y2  
 
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