Difference: TLUfirmware (22 vs. 23)

Revision 232018-03-02 - AtlasjSilicon

 
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TLUfirmware


TLUadapter board

TLUadapter board ver.B-> 表、-> 裏

adapter boardのNIMinは50 ohm terminationが必要となるので、 別途実装する

設計ミスでSEABASのJ1とJ3どちらか片方にしか接続できない問題(新しいものでは解決済み)

Kyocera connector側：NIMinが回路図と反対側に繋がっていた->不幸なことに一部がADCと繋がっている(FPGAと繋がっていない)J3 connector側であり、SEABAS上での接続先がそのADCにあてがわれていた

Integration testではJ3に接続するつもりだったconnectorをSEABAS側J2に接続する(J1は未接続、JTAGが干渉してadapter boardはSEABASにしっかりとは刺さっていない)

SEABASのFPGAではLVDS信号は扱えない(ucfファイルで指定しようとすると怒られる)のでB'版ではLVDS->CMOSのICを実装する

波形が出ない場合はPIN assignが間違っていないか確認する

->基本的にucfファイルを編集する。どのPINが何に使われているかを一覧で見たい場合はPlanAheadを起動すると分かりやすい

https://docs.google.com/spreadsheets/d/12SCUal2avY3kW65fRVte5TG3hSL1h8-VrYYAfBwH4Lk/edit?usp=sharing

接続 信号名 silk in/out signal J2 FPGA notes
NIMin4 NIMin[4]   in NIM D79 N2  
NIMin5 NIMin[5]   in NIM D78 N1 not implemented
NIMin6 NIMin[6]   in NIM D77 P1 not implemented
NIMin7 NIMin[7]   in NIM D76 P3 not implemented
NIMout2 NIMout[2] NIMout3 out NIM D75 P4  
NIMout3 NIMout[3] NIMout2 out NIM D74 P5  
NIMout4 NIMout[4] NIMout? out NIM D73 R1  
NIMout5 NIMout[5] NIMout4 out NIM D72 R2  
dout0_p dout0[0] MPPC1_1 in (LVDS) D52 L3 not implemented
dout0_n dout0[1] in (LVDS) D53 L2
dout_cmos0   in (TTL) D54 M5
DAC_LDACn0   out   D55 M4
dout1_p dout1[0] MPPC2_1 in (LVDS) D44 J3  
dout1_n dout1[1] in (LVDS) D45 J1  
dout_cmos1   in (TTL) D46 K5  
DAC_LDACn1   out   D47 K3  
DAC_PREn1   out   D48 K2  
DAC_FS1   out   D49 K1  
DAC_DIN1   out   D50 L5  
DAC_SCLK1   out   D51 L4  
dout2_p dout2[0] MPPC2 in (LVDS) D63 U4 not implemented
dout2_n dout2[1] in (LVDS) D62 U5
dout_cmos2   in (TTL) D61 V1
DAC_LDACn2   out   D60 V2
DAC_PREn2   out   D40 H2
DAC_FS2   out   D41 H1
DAC_DIN2   out   D42 J5
DAC_SCLK2   out   D43 J4
dout3_p dout3[0] MPPC3 in (LVDS) D71 R3 not implemented
dout3_n dout3[1] in (LVDS) D70 R5
dout_cmos3   in (TTL) D69 T2
DAC_LDACn3   out   D68 T3
DAC_PREn3   out   D67 T4
DAC_FS3   out   D66 T5
DAC_DIN3   out   D65 U1
DAC_SCLK3   out   D64 U2
ADC_P14 LVCMOSin[0] CMOSin6 in   D56 M2

special connection for CMOSin

HSIO2 busy
ADC_N14 LVCMOSout[0] CMOSout0 out   D57 M1

special connection for CMOSout

HSIO2 exttrigger
Changed:
<
<		本番用
>
>		本番用(3/1更新)
 
接続 信号名 silk in/out J1 FPGA comments     信号名 信号名 silk in/out J3 FPGA comments
CMOSin0 LVCMOSin[0]   in D0 E10 HSIO2 busy     NIMin4 NIMin[4]   in D96 AB4 ROI
Changed:
<
<
CMOSin1 LVCMOSin[1]   in D1 A8 Pico Gen()     NIMin5 NIMin[5]   in D97 AB5 SVX busy
>
>
CMOSin1 LVCMOSin[1]   in D1 A8 Pico Gen(no signal)     NIMin5 NIMin[5]   in D97 AB5 SVX busy
 
CMOSin2 LVCMOSin[2]   in D2 C8       NIMin6 NIMin[6]   in D98 AC1 DRS4 busy
CMOSin3 LVCMOSin[3]   in D3 D8       NIMin7 NIMin[7]   in D99 AC2  
CMOSin4 LVCMOSin[4]   in D4 A7       NIMout2 NIMout[2]   out D115 AC3 NIMin[4]
CMOSin5 LVCMOSin[5]   in D5 B7       NIMout3 NIMout[3]   out D114 AC4 LGAD trigger(TrigBeam)
CMOSin6 LVCMOSin[6]   in D6 C7       NIMout4 NIMout[4]   out D113 AD1 SVX4 timestamp CLK100K
CMOSout0 LVCMOSout[0]   out D7 B6 NIMin[5]     NIMout5 NIMout[5]   out D112 AD3 SVX4 trigger(TrigBeam)
CMOSout1 LVCMOSout[1]   out D8 C6 busy OR     dout0 dout[0] MPPCctl1 in D92 AA4  
CMOSout2 LVCMOSout[2]   out D9 D6 Pico Ext(TrigBeam)     dout_cmos0   in D94 AB1  
CMOSout3 LVCMOSout[3]   out D10 A5 Pico D(TrigBeam)     DAC_LDACn0   out D95 AB2  
CMOSout4 LVCMOSout[4]   out D11 B5 TrigBeam     dout1 dout[1] MPPCctl2 in D84 W4  
CMOSout5 LVCMOSout[5]   out D12 D5 TrigBeam     dout_cmos1   in D85 W5  
CMOSout6 LVCMOSout[6]   out D13 A4 busy OR     DAC_LDACn1   out D87 Y2  
CMOSout7 LVCMOSout[7]   out D14 B4 TrigBeam     DAC_PREn1   out D88 Y3  
CMOSout8 LVCMOSout[8]   out D15 C4 HSIO2 trigger(TrigBeam)     DAC_FS1   out D89 Y5  
LVDS1in LVDSin[0] RJ45_0 in D23 G2       DAC_DIN1   out D90 AA2  
LVDS2out LVDSout[0] out D22 G1 TrigBeam     DAC_SCLK1   out D91 AA3  
LVDS3in LVDSin[1] in D21 H4       dout2 dout[2] MPPCctl3 in D103 AE3  
LVDS4out LVDSout[1] out D20 H3 TrigBeam     dout_cmos2   in D101 AD6  
GPIO5 GPIO[5] GPIO1   D27 F3       DAC_LDACn2   out D100 AE6  
GPIO6 GPIO[6]   D28 F4       DAC_PREn2   out D80 V3  
GPIO7 GPIO[7]   D26 F2       DAC_FS2   out D81 V4  
GPIO8 GPIO[8]   D29 F5       DAC_DIN2   out D82 W1  
GPIO9 GPIO[9]   D25 G5       DAC_SCLK2   out D83 W3  
GPIO10 GPIO[10]   D30 E1       dout3 dout[3] MPPCctl4 in D111 AE1  
GPIO11 GPIO[11]   D24 G4       dout_cmos3   in D109 AE5  
GPIO12 GPIO[12]   D31 E2       DAC_LDACn3   out D108 AF2  
DAC_PREn0   MPPCctl1 out D39 C3       DAC_PREn3   out D107 AB7  
DAC_FS0   out D38 C2       DAC_FS3   out D106 AF3  
DAC_DIN0   out D37 C1       DAC_DIN3   out D105 AF4  
DAC_SCLK0   out D36 D4       DAC_SCLK3   out D104 AD5  

Firmware

SeabasTLU-FNAL2/FirmwareSeabasTLU-trunk.xiseがSeabasTLUのprojectファイル

SeabasTLU.png

ファイルに変更を加えた場合は上書き保存(ISEなら左上[Edit]下のフロッピーアイコンをクリック)する

コンパイルは、ViewがImplementationになっているのを確認してTLU_topを選択。

how to use ISE Hide 
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############コンパイルの仕方############

Screenshot-2.png

Screenshot.png

Screenshot-1.png

↑のようになっていればコンパイルは成功している

############FPGAへの焼き方############

Screenshot-3.png

そうすると別ウィンドウでISE iMPACTが立ち上がる

以降はSEABASがJtagで接続されていることを前提としている

Screenshot-4.png

Screenshot-5.png

Screenshot-11.pngScreenshot-6.pngScreenshot-7.pngScreenshot-8.pngScreenshot-9.pngScreenshot-10.png 

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DAC firmware

実装DAC-> TLV5630

-- Atlasj Silicon - 2018-01-31

Comments 


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