(r13) TLUfirmware < Main

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---+ TLUfirmware

<br />%TOC%
---++ TLUadapter board

TLUadapter board ver.B-&gt; [[%ATTACHURL%/DSC_0003.jpg][&#x8868;]]&#x3001;-&gt; [[%ATTACHURL%/DSC_0001.jpg][&#x88CF;]]

adapter board&#x306E;NIMin&#x306F;50 ohm termination&#x304C;%RED%&#x5FC5;&#x8981;&#x3068;&#x306A;&#x308B;%ENDCOLOR%&#x306E;&#x3067;&#x3001; [[%ATTACHURL%/DSC_0004.JPG][&#x5225;&#x9014;&#x5B9F;&#x88C5;]]&#x3059;&#x308B;

&#x8A2D;&#x8A08;&#x30DF;&#x30B9;&#x3067;SEABAS&#x306E;J1&#x3068;J3&#x3069;&#x3061;&#x3089;&#x304B;&#x7247;&#x65B9;&#x306B;&#x3057;&#x304B;&#x63A5;&#x7D9A;&#x3067;&#x304D;&#x306A;&#x3044;&#x554F;&#x984C;(&#x65B0;&#x3057;&#x3044;&#x3082;&#x306E;&#x3067;&#x306F;&#x89E3;&#x6C7A;&#x6E08;&#x307F;)

Kyocera connector&#x5074;&#xFF1A;NIMin&#x304C;&#x56DE;&#x8DEF;&#x56F3;&#x3068;&#x53CD;&#x5BFE;&#x5074;&#x306B;&#x7E4B;&#x304C;&#x3063;&#x3066;&#x3044;&#x305F;-&gt;&#x4E0D;&#x5E78;&#x306A;&#x3053;&#x3068;&#x306B;&#x4E00;&#x90E8;&#x304C;ADC&#x3068;&#x7E4B;&#x304C;&#x3063;&#x3066;&#x3044;&#x308B;(FPGA&#x3068;&#x7E4B;&#x304C;&#x3063;&#x3066;&#x3044;&#x306A;&#x3044;)J3 connector&#x5074;&#x3067;&#x3042;&#x308A;&#x3001;SEABAS&#x4E0A;&#x3067;&#x306E;&#x63A5;&#x7D9A;&#x5148;&#x304C;&#x305D;&#x306E;ADC&#x306B;&#x3042;&#x3066;&#x304C;&#x308F;&#x308C;&#x3066;&#x3044;&#x305F;

Integration test&#x3067;&#x306F;J3&#x306B;&#x63A5;&#x7D9A;&#x3059;&#x308B;&#x3064;&#x3082;&#x308A;&#x3060;&#x3063;&#x305F;connector&#x3092;SEABAS&#x5074;J2&#x306B;&#x63A5;&#x7D9A;&#x3059;&#x308B;(J1&#x306F;&#x672A;&#x63A5;&#x7D9A;&#x3001;JTAG&#x304C;&#x5E72;&#x6E09;&#x3057;&#x3066;adapter board&#x306F;SEABAS&#x306B;&#x3057;&#x3063;&#x304B;&#x308A;&#x3068;&#x306F;&#x523A;&#x3055;&#x3063;&#x3066;&#x3044;&#x306A;&#x3044;)

SEABAS&#x306E;FPGA&#x3067;&#x306F;LVDS&#x4FE1;&#x53F7;&#x306F;&#x6271;&#x3048;&#x306A;&#x3044;(ucf&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x3067;&#x6307;&#x5B9A;&#x3057;&#x3088;&#x3046;&#x3068;&#x3059;&#x308B;&#x3068;&#x6012;&#x3089;&#x308C;&#x308B;)&#x306E;&#x3067;B'&#x7248;&#x3067;&#x306F;LVDS-&gt;CMOS&#x306E;IC&#x3092;&#x5B9F;&#x88C5;&#x3059;&#x308B;

&#x6CE2;&#x5F62;&#x304C;&#x51FA;&#x306A;&#x3044;&#x5834;&#x5408;&#x306F;PIN assign&#x304C;&#x9593;&#x9055;&#x3063;&#x3066;&#x3044;&#x306A;&#x3044;&#x304B;&#x78BA;&#x8A8D;&#x3059;&#x308B;

-&gt;&#x57FA;&#x672C;&#x7684;&#x306B;ucf&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x3092;&#x7DE8;&#x96C6;&#x3059;&#x308B;&#x3002;&#x3069;&#x306E;PIN&#x304C;&#x4F55;&#x306B;&#x4F7F;&#x308F;&#x308C;&#x3066;&#x3044;&#x308B;&#x304B;&#x3092;&#x4E00;&#x89A7;&#x3067;&#x898B;&#x305F;&#x3044;&#x5834;&#x5408;&#x306F;PlanAhead&#x3092;&#x8D77;&#x52D5;&#x3059;&#x308B;&#x3068;&#x5206;&#x304B;&#x308A;&#x3084;&#x3059;&#x3044;

*[[https://docs.google.com/spreadsheets/d/12SCUal2avY3kW65fRVte5TG3hSL1h8-VrYYAfBwH4Lk/edit?usp=sharing]]*
| *&#x63A5;&#x7D9A;* | *&#x4FE1;&#x53F7;&#x540D;* | *silk* | *in/out* | *signal* | *J2* | *FPGA* | *notes* |
| NIMin4 | NIMin[4] | | in | NIM | D79 | N2 | |
| NIMin5 | NIMin[5] | | in | NIM | D78 | N1 | not implemented |
| NIMin6 | NIMin[6] | | in | NIM | D77 | P1 | not implemented |
| NIMin7 | NIMin[7] | | in | NIM | D76 | P3 | not implemented |
| NIMout2 | NIMout[2] | NIMout3 | out | NIM | D75 | P4 | |
| NIMout3 | NIMout[3] | NIMout2 | out | NIM | D74 | P5 | |
| NIMout4 | NIMout[4] | NIMout? | out | NIM | D73 | R1 | |
| NIMout5 | NIMout[5] | NIMout4 | out | NIM | D72 | R2 | |
| dout0_p | dout0[0] | MPPC1_1 | in | (LVDS) | D52 | L3 | not implemented |
| dout0_n | dout0[1] | ^ | in | (LVDS) | D53 | L2 | ^ |
| dout_cmos0 | | ^ | in | (TTL) | D54 | M5 | ^ |
| DAC_LDACn0 | | ^ | out | | D55 | M4 | ^ |
| dout1_p | dout1[0] | MPPC2_1 | in | (LVDS) | D44 | J3 | |
| dout1_n | dout1[1] | ^ | in | (LVDS) | D45 | J1 | |
| dout_cmos1 | | ^ | in | (TTL) | D46 | K5 | |
| DAC_LDACn1 | | ^ | out | | D47 | K3 | |
| DAC_PREn1 | | ^ | out | | D48 | K2 | |
| DAC_FS1 | | ^ | out | | D49 | K1 | |
| DAC_DIN1 | | ^ | out | | D50 | L5 | |
| DAC_SCLK1 | | ^ | out | | D51 | L4 | |
| dout2_p | dout2[0] | MPPC2 | in | (LVDS) | D63 | U4 | not implemented |
| dout2_n | dout2[1] | ^ | in | (LVDS) | D62 | U5 | ^ |
| dout_cmos2 | | ^ | in | (TTL) | D61 | V1 | ^ |
| DAC_LDACn2 | | ^ | out | | D60 | V2 | ^ |
| DAC_PREn2 | | ^ | out | | D40 | H2 | ^ |
| DAC_FS2 | | ^ | out | | D41 | H1 | ^ |
| DAC_DIN2 | | ^ | out | | D42 | J5 | ^ |
| DAC_SCLK2 | | ^ | out | | D43 | J4 | ^ |
| dout3_p | dout3[0] | MPPC3 | in | (LVDS) | D71 | R3 | not implemented |
| dout3_n | dout3[1] | ^ | in | (LVDS) | D70 | R5 | ^ |
| dout_cmos3 | | ^ | in | (TTL) | D69 | T2 | ^ |
| DAC_LDACn3 | | ^ | out | | D68 | T3 | ^ |
| DAC_PREn3 | | ^ | out | | D67 | T4 | ^ |
| DAC_FS3 | | ^ | out | | D66 | T5 | ^ |
| DAC_DIN3 | | ^ | out | | D65 | U1 | ^ |
| DAC_SCLK3 | | ^ | out | | D64 | U2 | ^ |
| ADC_P14 | LVCMOSin[0] | CMOSin6 | in | | D56 | M2 | <p>special connection for CMOSin</p> <p>HSIO2 busy</p> |
| ADC_N14 | LVCMOSout[0] | CMOSout0 | out | | D57 | M1 | <p>special connection for CMOSout</p> <p>HSIO2 exttrigger</p> |

&#x672C;&#x756A;&#x7528;
| *&#x63A5;&#x7D9A;* | *&#x4FE1;&#x53F7;&#x540D;* | *silk* | *in/out* | *J1* | *FPGA* | | | *&#x4FE1;&#x53F7;&#x540D;* | *&#x4FE1;&#x53F7;&#x540D;* | *silk* | *in/out* | *J3* | *FPGA* |
| CMOSin0 | LVCMOSin[0] | | in | D0 | E10 | | | NIMin4 | NIMin[4] | | in | D99 | AC2 |
| CMOSin1 | LVCMOSin[1] | | in | D1 | A8 | | | NIMin5 | NIMin[5] | | in | D98 | AC1 |
| CMOSin2 | LVCMOSin[2] | | in | D2 | C8 | | | NIMin6 | NIMin[6] | | in | D97 | AB5 |
| CMOSin3 | LVCMOSin[3] | | in | D3 | D8 | | | NIMin7 | NIMin[7] | | in | D96 | AB4 |
| CMOSin4 | LVCMOSin[4] | | in | D4 | A7 | | | NIMout2 | NIMout[2] | NIMout3 | out | D115 | AC3 |
| CMOSin5 | LVCMOSin[5] | | in | D5 | B7 | | | NIMout3 | NIMout[3] | NIMout2 | out | D114 | AC4 |
| CMOSin6 | LVCMOSin[6] | | in | D6 | C7 | | | NIMout4 | NIMout[4] | NIMout? | out | D113 | AD1 |
| CMOSout0 | LVCMOSout[0] | | out | D7 | B6 | | | NIMout5 | NIMout[5] | NIMout4 | out | D112 | AD3 |
| CMOSout1 | LVCMOSout[1] | | out | D8 | C6 | | | dout0_p | dout0[0] | MPPC1_1 | in | D92 | AA4 |
| CMOSout2 | LVCMOSout[2] | | out | D9 | D6 | | | dout0_n | dout0[1] | ^ | in | D93 | AA5 |
| CMOSout3 | LVCMOSout[3] | | out | D10 | A5 | | | dout_cmos0 | | ^ | in | D94 | AB1 |
| CMOSout4 | LVCMOSout[4] | | out | D11 | B5 | | | DAC_LDACn0 | | ^ | out | D95 | AB2 |
| CMOSout5 | LVCMOSout[5] | | out | D12 | D5 | | | dout1_p | dout1[0] | MPPC2_1 | in | D84 | W4 |
| CMOSout6 | LVCMOSout[6] | | out | D13 | A4 | | | dout1_n | dout1[1] | ^ | in | D85 | W5 |
| CMOSout7 | LVCMOSout[7] | | out | D14 | B4 | | | dout_cmos1 | | ^ | in | D86 | Y1 |
| CMOSout8 | LVCMOSout[8] | | out | D15 | C4 | | | DAC_LDACn1 | | ^ | out | D87 | Y2 |
| LVDS1in | LVDSin[0] | LVDS | in | D23 | G2 | | | DAC_PREn1 | | ^ | out | D88 | Y3 |
| LVDS2out | LVDSout[0] | ^ | out | D22 | G1 | | | DAC_FS1 | | ^ | out | D89 | Y5 |
| LVDS3in | LVDSin[1] | ^ | in | D21 | H4 | | | DAC_DIN1 | | ^ | out | D90 | AA2 |
| LVDS4out | LVDSout[1] | ^ | out | D20 | H3 | | | DAC_SCLK1 | | ^ | out | D91 | AA3 |
| GPIO5 | GPIO[5] | GPIO1 | | D27 | F3 | | | dout2_p | dout2[0] | MPPC2 | in | D103 | AE3 |
| GPIO6 | GPIO[6] | ^ | | D28 | F4 | | | dout2_n | dout2[1] | ^ | in | D102 | AF5 |
| GPIO7 | GPIO[7] | ^ | | D26 | F2 | | | dout_cmos2 | | ^ | in | D101 | AD6 |
| GPIO8 | GPIO[8] | ^ | | D29 | F5 | | | DAC_LDACn2 | | ^ | out | D100 | AE6 |
| GPIO9 | GPIO[9] | ^ | | D25 | G5 | | | DAC_PREn2 | | ^ | out | D80 | V3 |
| GPIO10 | GPIO[10] | ^ | | D30 | E1 | | | DAC_FS2 | | ^ | out | D81 | V4 |
| GPIO11 | GPIO[11] | ^ | | D24 | G4 | | | DAC_DIN2 | | ^ | out | D82 | W1 |
| GPIO12 | GPIO[12] | ^ | | D31 | E2 | | | DAC_SCLK2 | | ^ | out | D83 | W3 |
| DAC_PREn0 | | MPPC1_1 | out | D36 | D4 | | | dout3_p | dout3[0] | MPPC2 | in | D111 | AE1 |
| DAC_FS0 | | ^ | out | D37 | C1 | | | dout3_n | dout3[1] | ^ | in | D110 | AE2 |
| DAC_DIN0 | | ^ | out | D38 | C2 | | | dout_cmos3 | | ^ | in | D109 | AE5 |
| DAC_SCLK0 | | ^ | out | D39 | C3 | | | DAC_LDACn3 | | ^ | out | D108 | AF2 |
| | | | | | | | | DAC_PREn3 | | ^ | out | D107 | AB7 |
| | | | | | | | | DAC_FS3 | | ^ | out | D106 | AF3 |
| | | | | | | | | DAC_DIN3 | | ^ | out | D105 | AF4 |
| | | | | | | | | DAC_SCLK3 | | ^ | out | D104 | AD5 |

---++ Firmware

SeabasTLU-FNAL2/FirmwareSeabasTLU-trunk.xise&#x304C;SeabasTLU&#x306E;project&#x30D5;&#x30A1;&#x30A4;&#x30EB;

<img alt="SeabasTLU.png" height="388" src="%ATTACHURL%/SeabasTLU.png" width="514" />

&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x306B;&#x5909;&#x66F4;&#x3092;&#x52A0;&#x3048;&#x305F;&#x5834;&#x5408;&#x306F;&#x4E0A;&#x66F8;&#x304D;&#x4FDD;&#x5B58;(ISE&#x306A;&#x3089;&#x5DE6;&#x4E0A;[Edit]&#x4E0B;&#x306E;&#x30D5;&#x30ED;&#x30C3;&#x30D4;&#x30FC;&#x30A2;&#x30A4;&#x30B3;&#x30F3;&#x3092;&#x30AF;&#x30EA;&#x30C3;&#x30AF;)&#x3059;&#x308B;

&#x30B3;&#x30F3;&#x30D1;&#x30A4;&#x30EB;&#x306F;&#x3001;View&#x304C;Implementation&#x306B;&#x306A;&#x3063;&#x3066;&#x3044;&#x308B;&#x306E;&#x3092;&#x78BA;&#x8A8D;&#x3057;&#x3066;TLU_top&#x3092;&#x9078;&#x629E;&#x3002;Synthesize-XST&#x3092;&#x30C0;&#x30D6;&#x30EB;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x307E;&#x305F;&#x306F;&#x53F3;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x3067;Run(ReRun)&#x3092;&#x30AF;&#x30EA;&#x30C3;&#x30AF;

Synthesize&#x304C;&#x7D42;&#x308F;&#x3063;&#x305F;&#x3089;&#x3001;Implement Design&#x3092;&#x30C0;&#x30D6;&#x30EB;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x307E;&#x305F;&#x306F;&#x53F3;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x3067;Run(ReRun)&#x3092;&#x30AF;&#x30EA;&#x30C3;&#x30AF;

&#x7D42;&#x308F;&#x3063;&#x305F;&#x3089;&#x3001;Generate Programming File&#x3092;&#x30C0;&#x30D6;&#x30EB;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x307E;&#x305F;&#x306F;&#x53F3;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x3067;Run(ReRun)&#x3092;&#x30AF;&#x30EA;&#x30C3;&#x30AF;

&#x3053;&#x3053;&#x307E;&#x3067;&#x3067;error <img alt="ISE_error.png" src="%ATTACHURL%/ISE_error.png" />&#x304C;&#x51FA;&#x306A;&#x3051;&#x308C;&#x3070;&#x30B3;&#x30F3;&#x30D1;&#x30A4;&#x30EB;&#x306F;&#x6210;&#x529F;&#x3057;&#x3066;&#x3044;&#x308B;&#x306E;&#x3067;&#x3001;Configure Target Device&#x5185;&#x306E;Manage Configuration Project (iMPACT)&#x3092;&#x30C0;&#x30D6;&#x30EB;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x3059;&#x308B;

ISE iMPACT(&#x5225;&#x30A6;&#x30A3;&#x30F3;&#x30C9;&#x30A6;)&#x304C;&#x7ACB;&#x3061;&#x4E0A;&#x304C;&#x3063;&#x305F;&#x3089;Boundary Scan&#x3092;&#x30C0;&#x30D6;&#x30EB;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x3057;&#x3066;&#x3001;&#x53F3;&#x5074;&#x306E;&#x7BC4;&#x56F2;&#x5185;&#x3067;&#x53F3;&#x30AF;&#x30EA;&#x30C3;&#x30AF;-&gt;Initialize Chain&#x3092;&#x30AF;&#x30EA;&#x30C3;&#x30AF;&#x3002;&#x305D;&#x3046;&#x3059;&#x308B;&#x3068;Seabas&#x306B;&#x4E57;&#x3063;&#x3066;&#x3044;&#x308B;FPGA&#x304C;&#x8A8D;&#x8B58;&#x3055;&#x308C;&#x308B;

TLU&#x306E;&#x30D7;&#x30ED;&#x30B0;&#x30E9;&#x30E0;&#x713C;&#x304F;FPGA&#x306F;&#x53F3;&#x5074;&#x306A;&#x306E;&#x3067;&#x305D;&#x3061;&#x3089;&#x3092;&#x9078;&#x629E;(&#x7DD1;&#x8272;&#x306B;&#x306A;&#x3063;&#x3066;&#x308C;&#x3070;OK)&#x3057;&#x3066;&#x3001;bit&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x3092;&#x6307;&#x5B9A;&#x3059;&#x308B;(&#x3053;&#x306E;&#x5F8C;&#x306B;&#x5225;&#x30A6;&#x30A3;&#x30F3;&#x30C9;&#x30A6;&#x3067;Device Programming Properties&#x304C;&#x51FA;&#x3066;&#x304D;&#x3066;&#x3082;&#x7279;&#x306B;&#x95A2;&#x4FC2;&#x306A;&#x3044;&#x306E;&#x3067;OK&#x3092;&#x9078;&#x629E;&#x3059;&#x308B;)

Program&#x3092;&#x30C0;&#x30D6;&#x30EB;&#x30AF;&#x30EA;&#x30C3;&#x30AF;-&gt;Program Succeeded&#x304C;&#x51FA;&#x308C;&#x3070;&#x5B8C;&#x4E86;&#xFF01;(PROM&#x306B;&#x66F8;&#x304D;&#x8FBC;&#x3080;&#x304B;&#x3068;&#x805E;&#x304B;&#x308C;&#x305F;&#x3089;No&#x3092;&#x9078;&#x629E;&#x3057;&#x3066;&#x4E0B;&#x3055;&#x3044;)
---+++ DAC firmware

&#x5B9F;&#x88C5;DAC-&gt; [[%ATTACHURL%/tlv5630.pdf][TLV5630]]

-- %USERSIG{AtlasjSilicon - 2018-01-31}%

---++ Comments

<br />%COMMENT%

Attachments

Topic attachments
I	Attachment	History	Action	Size	Date	Who
pdf	110520seabas2a.pdf	r1	manage	454.4 K	2018-01-31 - 06:14	AtlasjSilicon
jpg	DSC_0001.jpg	r1	manage	1276.9 K	2018-01-31 - 12:45	AtlasjSilicon
jpg	DSC_0003.jpg	r1	manage	999.0 K	2018-01-31 - 12:45	AtlasjSilicon
jpg	DSC_0004.JPG	r1	manage	307.3 K	2018-02-09 - 14:56	AtlasjSilicon
png	ISE_error.png	r1	manage	0.5 K	2018-02-03 - 08:23	AtlasjSilicon
png	ISE_ok.png	r1	manage	0.6 K	2018-02-03 - 08:23	AtlasjSilicon
png	ISE_warning.png	r1	manage	0.5 K	2018-02-03 - 08:23	AtlasjSilicon
png	Screenshot-1.png	r1	manage	195.6 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-2.png	r1	manage	178.4 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-3.png	r1	manage	199.9 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-4.png	r1	manage	35.4 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-5.png	r1	manage	50.4 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-6.png	r1	manage	65.7 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-7.png	r1	manage	93.5 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-8.png	r1	manage	78.8 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot-9.png	r1	manage	68.6 K	2018-02-13 - 02:51	AtlasjSilicon
png	Screenshot.png	r1	manage	197.7 K	2018-02-13 - 02:51	AtlasjSilicon
png	SeabasTLU.png	r1	manage	33.9 K	2018-02-03 - 08:23	AtlasjSilicon
pdf	tlv5630.pdf	r1	manage	1155.8 K	2018-01-31 - 06:14	AtlasjSilicon

Topic revision: r13 - 2018-02-13 - AtlasjSilicon

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