RD53ADAQdevel < Main

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---+ !RD53ADAQdevel

&#x30E1;&#x30E2;

&#x30B3;&#x30F3;&#x30D1;&#x30A4;&#x30EB;&#x306B;&#x306F;Xilinx vivado 2019.2&#x304C;&#x5FC5;&#x8981;2019.1&#x3067;&#x306F;error&#x304C;&#x304A;&#x304D;&#x305F;&#x3002;

Platform Cable USB&#x2161;&#x304C;&#x5FC5;&#x8981;&#x3002;Platform Cable USB&#x3067;&#x306F;&#x5931;&#x6557;&#x3002;
---+ &#x713C;&#x304D;&#x65B9;

source /opt/Xilinx/Vivado/2019.2/settings64.sh

cd YARR-FW/script

cp &lt;bitfile/you/want/to/flash&gt; Download/

source flash.sh

<span style="background-color: transparent; color: #630000; font-size: 17.29px; font-weight: bold;">devel branch&#x3067;&#x306E;&#x30B3;&#x30F3;&#x30D1;&#x30A4;&#x30EB;</span>

source /opt/Xilinx/Vivado/2019.2/settings64.sh

git clone <a href="https://gitlab.cern.ch/YARR/YARR-FW.git" target="_blank">https://gitlab.cern.ch/YARR/YARR-FW.git</a>

cd YARR-FW

git checkout devel

cd syn/kintex7/

make hdl

# if no hdlmake installed type : sudo pip3 install hdlmake

make all -j4

&#x30E1;&#x30E2;

xpressk7-fmc-ohio.xdc :xpressk7&#x306E;&#x30D4;&#x30F3;&#x540D;&#x3068;&#x30D7;&#x30ED;&#x30B0;&#x30E9;&#x30E0;&#x5185;&#x3067;&#x306E;&#x4FE1;&#x53F7;&#x7DDA;&#x306E;&#x540D;&#x524D;&#x3092;&#x7D50;&#x3073;&#x3064;&#x3051;&#x308B;

bram_yarr_trenz.vhd :xpressk7&#x306E;&#x4FE1;&#x53F7;&#x7DDA;&#x3068;FPGA&#x5185;&#x90E8;&#x306E;&#x4FE1;&#x53F7;&#x3092;&#x3064;&#x306A;&#x3052;&#x308B;

app.vhd :FPGA&#x5185;&#x90E8;&#x306E;&#x306A;&#x3093;&#x304B;?
---+++ attach board&#x306E;RJ45&#x304B;&#x3089;&#x30C8;&#x30EA;&#x30AC;&#x30FC;&#x53D7;&#x3051;&#x53D6;&#x308A;

attach board &#x306E;RJ45&#x3067;&#x30C8;&#x30EA;&#x30AC;&#x30FC;&#x4FE1;&#x53F7;&#x3092;&#x53D7;&#x3051;&#x53D6;&#x3063;&#x305F;FW&#x306E;bitfile

/home/dharada/work/RD53A/YARR-FW/syn/kintex7/rd53_ohio_4x4_160Mbps/rd53_ohio_4x4_160Mbps_xpressk7_325.bit

&#x5909;&#x66F4;&#x70B9;

bram_yarr_trenz.vhd&#x306E;ext_trig_i_p,n&#x306E;&#x30B3;&#x30E1;&#x30F3;&#x30C8;&#x30A2;&#x30A6;&#x30C8;&#x3092;&#x5916;&#x3059;&#x3002;
---+++ attach board&#x306E;port&#x304B;&#x3089;&#x8AAD;&#x307F;&#x51FA;&#x3057;

&#x5358;&#x7D14;&#x306B;xpressk7-fmc-ohio.xdc&#x306E;pin&#x3092;Ohio board&#x306E;port A&#x3068;attack board&#x306E;port E&#x3092;&#x5165;&#x308C;&#x66FF;&#x3048;&#x3066;&#x307F;&#x305F;&#x304C;&#x8AAD;&#x307F;&#x51FA;&#x3057;&#x304C;&#x3067;&#x304D;&#x306A;&#x304B;&#x3063;&#x305F;&#x3002;
---+++ chipscope&#x306E;&#x4F7F;&#x3044;&#x65B9;

source /opt/Xilinx/Vivado/2019.2/settings64.sh

vivado

Open project&#x3067;xpr&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x3092;&#x9078;&#x629E;&#x3059;&#x308B;

&#x30FB;&#x898B;&#x308B;&#x4FE1;&#x53F7;&#x306E;&#x9078;&#x629E;

Open Synthesized Design&#x3092;&#x5B9F;&#x884C;

Set up Debug&#x3092;&#x5B9F;&#x884C;

Find Nets to Add...&#x304B;&#x3089;&#x4FE1;&#x53F7;&#x3092;&#x9078;&#x629E;

Next&#x3067;&#x30B5;&#x30F3;&#x30D7;&#x30EB;&#x6570;&#x3092;&#x9078;&#x629E;

Finish&#x3067;&#x7D42;&#x4E86;&#x3059;&#x308B;

&#x30FB;Debug&#x306E;&#x5B9F;&#x88C5;&#x3068;&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x4F5C;&#x6210;

Run Imprementation&#x3092;&#x5B9F;&#x884C;

Generate Bitstream&#x3092;&#x5B9F;&#x884C;

&#x30FB;FPGA&#x306B;&#x713C;&#x304F;

Open Hardware Manager

Open target , Auto connect

Bitstream file&#x306B;bit&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x3001;Debug probes file&#x306B;&#x3055;&#x3063;&#x304D;&#x4F5C;&#x3063;&#x305F;ltx&#x30D5;&#x30A1;&#x30A4;&#x30EB;&#x3092;&#x9078;&#x629E;

Program

&#x30FB;&#x4FE1;&#x53F7;&#x3092;&#x898B;&#x308B;

Hardware&#x304B;&#x3089;&#x898B;&#x305F;&#x3044;&#x4FE1;&#x53F7;&#x3092;&#x9078;&#x629E;

waveform&#x53F3;&#x4E0B;&#x306E;Trigger&#x306E;&#x3068;&#x3053;&#x308D;&#x306B;&#x898B;&#x305F;&#x3044;&#x4FE1;&#x53F7;&#x3092;&#x30C9;&#x30E9;&#x30C3;&#x30B0;

Trigger&#x4FE1;&#x53F7;&#x3092;&#x9078;&#x629E;

Run trigger for this ILA core (&#x25B6;&#xFE0E;&#x306E;&#x30DE;&#x30FC;&#x30AF;)

-- %USERSIG{DaigoHarada - 2020-08-17}%

---++ Comments

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Topic revision: r5 - 2020-09-26 - KojiNakamura