FE65p2ChipDAQ < Main

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---+ DAQ development for FE65-P2 chip

<br />%TOC%
---++ Introduction

FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the !RD53A/B chips used by HL-LHC ITK pixel upgrade.

more information is available in :

[[https://indico.cern.ch/event/521362/contributions/2135945/attachments/1259134/1860052/AUW_KEK_Pixel_20160418.pdf][motivation talk in AUW April 2016]]

[[https://indico.cern.ch/event/521370/contributions/2135196/attachments/1260660/1863032/2016_04_20-fe65p2-status_theim.pdf][Timon's talk in AUW April 2016]]

[[https://twiki.cern.ch/twiki/bin/view/Main/TimonHeim?forceShow=1][Timon's Twiki]]

[[%ATTACHURL%/FE65-P2.pdf][FE65-P2.pdf]]
---++ Chips and Bump Bonding at SLAC

<br />sensor name,bias(type), condition, patch work, dose,
| name  | bias structure(type) | condition | patch work | dose | comment |
| KEKFE65-1 | | | | | |
| KEKFE65-2 | | | | | |
| KEKFE65-3 | | | | | |
| KEKFE65-4 | | | | | |
| KEKFE65-5 | | | | | |
| KEKFE65-6 | no bias structure | | no | 3e15 | |
| KEKFE65-7 | no bias structure | no hit (digitalscan) | | | |
| KEKFE65-8 | poly-Si (type2) | missing bumpbonds at right top corner | no | 3e15 | register: PreCompVbnDac 50-&gt;35, PreampVbnFoldac -&gt;200 , Vffdaq 25-&gt;15<br />preampvbp-&gt;250 ::: good |
| KEKFE65-9 | poly-Si (type1) | | compVBAndaq,<br />priampVbnFolDac | 3e15 | |
| KEKFE65-10 | poly-Si (type6) | bottom half no hit (analogscan) | unknown | 3e15 | patch work...1,2,4,7 (Vthin1 80, Vthin2 60) |
| KEKFE65-11 | poly-Si (type8) | | unknown | 3e15 | External voltage(digital 1.2V, analog 1.2V) is necessary. |
| KEKFE65-12 | poly-Si (type2) | | Prmp150 | | pixel size 50*50 |
| KEKFE65-13 | no bias (type5) | | Prmp150 | | pixel size 50*50 |
| KEKFE65-14 | PT (type3) | | Prmp200 | | pixel size 50*50 |
| KEKFE65-15 | PT no space (type10) | | Prmp200 | | pixel size 50*50<br /> leakage increase roughly in proportion to HV |
| KEKFE65-16 | no bias (type8) | | Prmp200 | | pixel size 25*100 |
| KEKFE65-17 | | | | | |
| KEKFE65-18 | | | | | |
| KEKFE65-19 | | | | | |
| KEKFE65-20 | | | | | |
---++ DAQ development by SPEC
   * Installed CERN !CentOS7 to pcatutt21.cern.ch
   * Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35
---+++ How to setup SPEC board
   * on SLC6 or !CentOS7
      * need devtoolset-2 for gcc48
   * install font for gnuplot <verbatim>sudo yum -y install xorg-x11-fonts-ISO8859*</verbatim>
   * install software and firmware from git
<verbatim style="padding-left: 30px;">mkdir -p /home/atlasj/work/SPEC/YARR 
cd /home/atlasj/work/SPEC/YARR/
git clone https://github.com/Yarr/Yarr.git
git fetch
git checkout fe65_p2
cd /home/atlasj/work/SPEC/YARR/Yarr/src/kernel
make
sudo make install
sudo depmod
cd ../ ; make</verbatim>

   * install driver and program firmware to the SPEC card FPGAsudo rmmod specDriver
<verbatim style="padding-left: 30px;">sudo modprobe  specDriver
bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
bin/test

bin/benchmarkDma </verbatim>
---++ How to configure chips and run scan
---+++ tuning
   1 source gcc4.8.2 <verbatim>source /opt/rh/devtool/set_2/enable</verbatim>
   1 write FPGA <verbatim>cd /home/atlasj/work/SPEC/Yarr/src
./bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit</verbatim>
   1 Delete fe65p2.json <verbatim>cd ~/work/SPEC/Yarr/src
rm -f fe65p2.json</verbatim>
   1 Digital scan <verbatim>./primlist/scan.sh digitalscan <KEKFE65-(module #)_th(threshold)></verbatim>
   1 Analog scan <verbatim>./primlist/scan.sh analogscan <KEKFE65-(module #)_th(threshold)></verbatim>
   1 Threshold scan <verbatim>./primlist/scan.sh thresholdscan <KEKFE65-(module #)_th(threshold)></verbatim>
   1 Grobal tuning<br />change Vthin1 and Vthin2 (fe65p2.json)<br />differential threshold: threshold=Vthin1-Vthin2 &#x203B;Vthin2&gt;25<br /><br />
   1 set thresold tuning target<br />edit Line147 in scanconsole65.cpp <verbatim>bookiie.setTargetThreshold(threshold) </verbatim>
   1 Local tuning <verbatim>./primlist/scan.sh tune_pixelthreshold <KEKFE65-(module #)_th(threshold)></verbatim>
---+++ General scan consol

---+++ HitOr self trigger scan

1. Run digital scan<br />2. Run analog scan<br />3. Prepare config:<br /> - Enable all pixels: # bin/config_fe65-p2 fe65p2.json (Overwrites config file)<br /> - Apply digital scan mask: # bin/applyMask fe65p2_ch0_digitalscan_EnMask.dat fe65p2.json<br /> - Copy masked config: # cp masked_fe65p2.json fe65p2.json<br /> - Apply analog scan mask: # bin/applyMask fe65p2_ch0_analogscan_EnMask.dat fe65p2.json<br /> - Copy masked config: # cp masked_fe65p2.json fe65p2.json<br />4. Run noise scan (~5min)<br />5. Apply noise mask:<br /> - Apply digital scan mask: # bin/applyMask fe65p2_ch0_noisescan_NoiseMask.dat fe65p2.json<br /> - Copy masked config: # cp masked_fe65p2.json fe65p2.json<br />6. Mask stuck/noise hitter pixels:<br /> - #bin/fixHitbus fe65p2.json (takes quite some time ~15min)<br /> - Only pixels which will get masked get printed to stdout, optimally these should not be many<br /> - If many pixels appear to not work something is wrong<br /> - You can observe the process by probing HitOr Output and Trigger, there should be two hitOr pulses per trigger<br /> - The program produces a mask hitbus_enMask.png<br /> - Copy masked config: # cp masked_fe65p2.json fe65p2.json<br />7. Run exttrigger scan:<br /> - If everything went right you should observe a trigger rate of a few Hz without a particle source<br /> - With source the rate should be much higher<br /> - The internal dead time is 200bc (currently hardcoded for testing)<br /><br />
---++ YARR DAQ in EUDAQ
<pre>Hi Koji,

See here for instructions on eudaq: <a href='http://yarr.readthedocs.io/en/eudaq/eudaq.html'>http://yarr.readthedocs.io/en/eudaq/eudaq.html</a>
Swap into branch “eudaq”. Don’t forget to program the correct firmware (assuming you already have the adapter board).

Some remarks:
- I had a merge conflict problem in the firmware and I’m not 100% that is resolvers properly. If it is not right, YARR would not answer to triggers, which you should see if the RC does not see more trigger.
- I had to change the way events get send to the RC, this is untested and I hope it works.
- There is a version of the converter, but I’m sure there were local changes and I can’t get onto the eudaq machine at SLAC due to some stupid permissions. We need to wait until someone sends me the file. 

If you give me a not to random time window in your night where I can test some things with, we could do that. I have to run some errants and will not be at my laptop the whole time.

Otherwise we can get everything running once I’m there in person.

Cheers,
Timon
</pre>

https://eutelescope.web.cern.ch/forum/multiple-dut-events-tlu-trigger

instructions on eudaq -&gt; http://yarr.readthedocs.io/en/latest/eudaq.html
---++ Exttrigger mode

Seabas firmware : <br />MPPC bias : ~60V<br />Latency : 70<br /><br />///// memo

KEKFE65-13@-20degC<br /><br />CompVbnDac: 50<br />PrempVbpDac: 120<br />VbnLccDac : 200<br />VffDac : 15

---++ !XpressK7 DAQ

FE65byXpressK7

---++ Images

<br />%IMAGEGALLERY{columns="4" limit="70" size="huge" }% There are %NRIMAGES{}% images in this page

-- %USERSIG{KojiNakamura - 2016-04-21}%
---++ Log note

AfterIrrad20161018

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pdf	FE65-P2.pdf	r1	manage	3349.7 K	2017-02-04 - 04:31	JunkiSuzuki
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Topic revision: r30 - 2017-12-08 - KojiNakamura