DAQ development for FE65-P2 chip


FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the RD53A/B chips used by HL-LHC ITK pixel upgrade.

more information is available in :

motivation talk in AUW April 2016

Timon's talk in AUW April 2016

Timon's Twiki


Chips and Bump Bonding at SLAC

sensor name,bias(type), condition, patch work, dose,

name bias structure(type) condition patch work dose comment
KEKFE65-6 no bias structure   no 3e15  
KEKFE65-7 no bias structure no hit (digitalscan)      
KEKFE65-8 poly-Si (type2) missing bumpbonds at right top corner no 3e15 register: PreCompVbnDac 50->35, PreampVbnFoldac ->200 , Vffdaq 25->15
preampvbp->250 ::: good
KEKFE65-9 poly-Si (type1)   compVBAndaq,
KEKFE65-10 poly-Si (type6) bottom half no hit (analogscan) unknown 3e15 patch work...1,2,4,7 (Vthin1 80, Vthin2 60)
KEKFE65-11 poly-Si (type8)   unknown 3e15 External voltage(digital 1.2V, analog 1.2V) is necessary.
KEKFE65-12 poly-Si (type2)   Prmp150   pixel size 50*50
KEKFE65-13 no bias (type5)   Prmp150   pixel size 50*50
KEKFE65-14 PT (type3)   Prmp200   pixel size 50*50
KEKFE65-15 PT no space (type10)   Prmp200   pixel size 50*50
leakage increase roughly in proportion to HV
KEKFE65-16 no bias (type8)   Prmp200   pixel size 25*100

DAQ development by SPEC

  • Installed CERN CentOS7 to pcatutt21.cern.ch
  • Installed SLC6 to keksipc01 : at KEK ip=

How to setup SPEC board

  • on SLC6 or CentOS7
    • need devtoolset-2 for gcc48
  • install font for gnuplot
    sudo yum -y install xorg-x11-fonts-ISO8859*
  • install software and firmware from git
mkdir -p /home/atlasj/work/SPEC/YARR 
cd /home/atlasj/work/SPEC/YARR/
git clone https://github.com/Yarr/Yarr.git
git fetch
git checkout fe65_p2
cd /home/atlasj/work/SPEC/YARR/Yarr/src/kernel
sudo make install
sudo depmod
cd ../ ; make

  • install driver and program firmware to the SPEC card FPGAsudo rmmod specDriver
sudo modprobe  specDriver
bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit


How to configure chips and run scan


  1. source gcc4.8.2
    source /opt/rh/devtool/set_2/enable
  2. write FPGA
    cd /home/atlasj/work/SPEC/Yarr/src
    ./bin/programFpga ../hdl/syn/yarr_fe65p2_revB.bit
  3. Delete fe65p2.json
    cd ~/work/SPEC/Yarr/src
    rm -f fe65p2.json
  4. Digital scan
    ./primlist/scan.sh digitalscan <KEKFE65-(module #)_th(threshold)>
  5. Analog scan
    ./primlist/scan.sh analogscan <KEKFE65-(module #)_th(threshold)>
  6. Threshold scan
    ./primlist/scan.sh thresholdscan <KEKFE65-(module #)_th(threshold)>
  7. Grobal tuning
    change Vthin1 and Vthin2 (fe65p2.json)
    differential threshold: threshold=Vthin1-Vthin2 ※Vthin2>25

  8. set thresold tuning target
    edit Line147 in scanconsole65.cpp
  9. Local tuning
    ./primlist/scan.sh tune_pixelthreshold <KEKFE65-(module #)_th(threshold)>

General scan consol

HitOr self trigger scan

1. Run digital scan
2. Run analog scan
3. Prepare config:
- Enable all pixels: # bin/config_fe65-p2 fe65p2.json (Overwrites config file)
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_digitalscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
- Apply analog scan mask: # bin/applyMask fe65p2_ch0_analogscan_EnMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
4. Run noise scan (~5min)
5. Apply noise mask:
- Apply digital scan mask: # bin/applyMask fe65p2_ch0_noisescan_NoiseMask.dat fe65p2.json
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
6. Mask stuck/noise hitter pixels:
- #bin/fixHitbus fe65p2.json (takes quite some time ~15min)
- Only pixels which will get masked get printed to stdout, optimally these should not be many
- If many pixels appear to not work something is wrong
- You can observe the process by probing HitOr Output and Trigger, there should be two hitOr pulses per trigger
- The program produces a mask hitbus_enMask.png
- Copy masked config: # cp masked_fe65p2.json fe65p2.json
7. Run exttrigger scan:
- If everything went right you should observe a trigger rate of a few Hz without a particle source
- With source the rate should be much higher
- The internal dead time is 200bc (currently hardcoded for testing)


Hi Koji,

See here for instructions on eudaq: http://yarr.readthedocs.io/en/eudaq/eudaq.html
Swap into branch ďeudaqĒ. Donít forget to program the correct firmware (assuming you already have the adapter board).

Some remarks:
- I had a merge conflict problem in the firmware and Iím not 100% that is resolvers properly. If it is not right, YARR would not answer to triggers, which you should see if the RC does not see more trigger.
- I had to change the way events get send to the RC, this is untested and I hope it works.
- There is a version of the converter, but Iím sure there were local changes and I canít get onto the eudaq machine at SLAC due to some stupid permissions. We need to wait until someone sends me the file. 

If you give me a not to random time window in your night where I can test some things with, we could do that. I have to run some errants and will not be at my laptop the whole time.

Otherwise we can get everything running once Iím there in person.



instructions on eudaq -> http://yarr.readthedocs.io/en/latest/eudaq.html

Exttrigger mode

Seabas firmware :
MPPC bias : ~60V
Latency : 70

///// memo


CompVbnDac: 50
PrempVbpDac: 120
VbnLccDac : 200
VffDac : 15

XpressK7 DAQ



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-- Koji Nakamura - 2016-04-21

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