Difference: RD53AtestAtLBL (1 vs. 2)

Revision 22018-02-17 - AtlasjSilicon

META TOPICPARENT	name="FermilabTestbeam2018"

RD53A test at LBL

git clone https://gitlab.cern.ch/YARR/YARR-FW.git

cd YARR-FW

git fetch
git checkout devel
git branch

cd scripts

./ip-160-325.sh

cd ../

cd syn/xpressk7

# modify file : app.vhd line 740

# add not for VHDCI card(lbnl passive). keep without "not" for Ohio card.

# I => not fe_cmd_o(I) -- Buffer input

cd ../../ ; cd rtl/kintex7/rx-core

# check file : aurora_rx_lane.vhd line 278

# in case Ohio or LBNL passive, keep datain_p as is. in case LBNL active, change this to datain_n

# din => datain_p,

# compile

# recommended : vivado 2016.2

cd syn/xpressk7/bram_rd53a_quad_lbnl-325/
make
--> rename bit file

# flash bit file to FPGA

python flash.py

--> choose file

git clone https://gitlab.cern.ch/YARR/YARR.git

cd YARR

git fetch
git checkout rd53a
cd src

make

# execute before testing chips

# test for DMA trasfer and clean up fifo

./bin/test

# digital injection for only 3 pixels.

./bin/rd53a_test

result is like :

[Data] : COL(12) ROW(0) PAR(1) TOT(15,11,15,11)
[Data] : COL(12) ROW(1) PAR(1) TOT(15,11,15,15)

# config file (not yet ready) : hard corded in :

libRd53a/Rd53aGlobalCfg.cpp

libRd53a/Rd53aPixelCfg.cpp

Added:

>
>

readpixreg & treshold scan (temp)

add file : rd53a_readpixreg.cpp rd53a_proto_thresholdscan.cpp in tools dir

add file : thresholdscan.sh in src dir

run : ./bin/readpixreg -r 100 -v

* note : need to take a look at the LV current since current get higher than normal due to fill non-zero bit to register (if you write 0x0707 for synchronous 0xffff for linear and differential to the all resister current is upto 0.8A)

Atlasj Silicon - 2018-02-16

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Revision 12018-02-16 - AtlasjSilicon

META TOPICPARENT	name="FermilabTestbeam2018"