(r3) FE65p2ChipDAQ < Main

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---+ DAQ development for FE65-P2 chip

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---++ Introduction

FE65-P2 is the readout ASIC with 65nm processing as pre-pre-production for the RD53A /B chips used by HL-LHC ITK pixel upgrade.

more information is available in :

[[https://indico.cern.ch/event/521362/contributions/2135945/attachments/1259134/1860052/AUW_KEK_Pixel_20160418.pdf][motivation talk in AUW April 2016]]

[[https://indico.cern.ch/event/521370/contributions/2135196/attachments/1260660/1863032/2016_04_20-fe65p2-status_theim.pdf][Timon's talk in AUW April 2016]]

[[https://twiki.cern.ch/twiki/bin/view/Main/TimonHeim?forceShow=1][Timon's Twiki]]
---++ Bump Bonding at SLAC
---++ DAQ development by SPEC
   * Installed CERN !CentOS7 to pcatutt21.cern.ch
   * Installed SLC6 to keksipc01 : at KEK ip=130.87.243.35

---++ Images
%IMAGEGALLERY{columns="4" limit="70" size="huge" }% There are %NRIMAGES{}% images in this page<br>

-- %USERSIG{KojiNakamura - 2016-04-21}%

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I	Attachment	History	Action	Size	Date	Who
jpg	DSC_1418.JPG	r1	manage	2926.0 K	2016-05-24 - 08:58	KojiNakamura
jpg	DSC_1420.JPG	r1	manage	3097.1 K	2016-05-24 - 08:58	KojiNakamura
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jpg	DSC_1459.JPG	r1	manage	3095.9 K	2016-05-24 - 08:58	KojiNakamura
jpg	DSC_1464.JPG	r1	manage	2777.3 K	2016-05-24 - 09:05	KojiNakamura
jpg	DSC_1466.JPG	r1	manage	3175.5 K	2016-05-24 - 09:05	KojiNakamura
jpg	DSC_1467.JPG	r1	manage	3063.4 K	2016-05-24 - 09:05	KojiNakamura
jpg	DSC_1505.JPG	r1	manage	3056.5 K	2016-05-24 - 09:09	KojiNakamura

Topic revision: r3 - 2016-05-24 - KojiNakamura

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