Difference:
Feb2019TestbeamLog
(12 vs. 13)
Revision 13
2019-02-21 -
AtlasjSilicon
Line: 1 to 1
META TOPICPARENT
name="FermilabTestbeamTop"
Feb2019TestbeamLog
2018/11/6
Line: 168 to 167
RD53 multi module readout test
[PM]
Added:
>
>
seabas
IN
OUT
NIM4
ROI trg
NIM3
DRS4 trg
CMOS0
HSIO2 busy
CMOS2
pico ext
LVDS0
MPPC
CMOS3
pico D
LVDS1
MPPC
CMOS8
HSIO2 trg
LVDS
RD53A
pico
A
B
C
D
ext
NIM dout
DRS4 busy?
CLK100K
CMOS dout
CMOS dout
2019/2/
[AM]
[PM]
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